Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Indira Seshadri"'
Autor:
Kanzo Kato, Lior Huli, Nathan Antonovich, David Hetzer, Steven Grzeskowiak, Eric Liu, Akiteru Ko, Satoru Shimura, Shinichiro Kawakami, Takahiro Kitano, Seiji Nagahara, Luciana Meli, Indira Seshadri, Martin Burkhardt, Karen Petrillo
Publikováno v:
Advances in Patterning Materials and Processes XL.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62f26d28be561703578290b2c86ae190
https://doi.org/10.1117/12.2657290
https://doi.org/10.1117/12.2657290
Autor:
Nathan Ip, Michael P. Belyansky, Christopher Netzband, Norifumi Kohama, Richard Johnson, Shobha Hosadurga, Jack Wong, John C. Arnold, Kisik Choi, Wai Kin Li, Indira Seshadri, Luciana Meli, Ilseok Son
Publikováno v:
Metrology, Inspection, and Process Control XXXVII.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ab2add2a7aa22fe31fe3d551e8514f40
https://doi.org/10.1117/12.2654679
https://doi.org/10.1117/12.2654679
Autor:
Eric R. Miller, Indira Seshadri, Tsung-Sheng Kang, Dominik Metzler, Joe Lee, Stuart Sieg, Sebastian U. Engelmann, Jeff Shearer, John Arnold, Nelson Felix
Publikováno v:
Advanced Etch Technology and Process Integration for Nanopatterning XI.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7953338e6e10af2ec81fea5d0521816e
https://doi.org/10.1117/12.2614316
https://doi.org/10.1117/12.2614316
Autor:
Curtis Durfee, Frougier Julien, Daniel Schmidt, Andrew M. Greene, Veeraraghavan S. Basker, Jennifer Church, Nelson Felix, Indira Seshadri, Mary Breton
Publikováno v:
Metrology, Inspection, and Process Control for Semiconductor Manufacturing XXXV.
Over the past several years, stacked Nanosheet Gate-All-Around (GAA) transistors captured the focus of the semiconductor industry and has been identified as the new lead architecture to continue LOGIC CMOS scaling beyond-5nm node. The fabrication of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9c6a4ecf9f0ad6d25b631e6567243b1c
https://doi.org/10.1117/12.2583636
https://doi.org/10.1117/12.2583636
Publikováno v:
Advanced Etch Technology and Process Integration for Nanopatterning X.
The ability to etch silicon highly anistropically at active fin heights of 45nm or greater is critical to fin patterning for continued CMOS scaling. Tight control of fin CD and taper is critical toward controlling the device, with particular importan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c558dd3b9077a67858070c9971af95fd
https://doi.org/10.1117/12.2583647
https://doi.org/10.1117/12.2583647
Autor:
Pietro Montanini, Stuart A. Sieg, Andrew M. Greene, Nelson Felix, Xu Wenyu, Daniel J. Dechene, Jingyun Zhang, Eric R. Miller, Yann Mignot, Carl J. Radens, Indira Seshadri, Praveen Joseph, Veeraraghavan S. Basker, Mary Breton, Tao Li
Publikováno v:
Design-Process-Technology Co-optimization for Manufacturability XIV.
Gate all around stacked nanosheet FET’s have emerged as the next technology to FinFET’s for beyond 7-nm scaling. With EUV technology integrated into manufacturing at 7nm, there is great interest to enable EUV direct print patterning for nanosheet
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c1657e32b8611133cff6f9ccc289143
https://doi.org/10.1117/12.2552159
https://doi.org/10.1117/12.2552159
Autor:
Kerem Akarvardar, Balasubramanian S. Haran, Dinesh Gupta, Juntao Li, Takashi Ando, Economikos Laertis, James J. Demarest, Andreas Knorr, Kai Zhao, Victor Chan, Ruqiang Bao, Cave Nigel, Huimei Zhou, Richard A. Conti, Veeraraghavan S. Basker, Andrew M. Greene, Huiming Bu, Miaomiao Wang, Robert R. Robison, Kanakasabapathy Sivananda K, Indira Seshadri, Chanro Park, Dechao Guo, Muthumanickam Sankarapandian, Ruilong Xie, Liying Jiang
Publikováno v:
2019 Symposium on VLSI Technology.
In this paper, we present for the first time a “Gate-Cut-Last” integration scheme completed within the Replacement Metal Gate (RMG) module. This novel gate cut (CT) technique allows the scaling of gate extension length past the end fin which redu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c79d17d97f0f8e79a50e6f8d02ad91d6
https://doi.org/10.23919/vlsit.2019.8776493
https://doi.org/10.23919/vlsit.2019.8776493
On Thermal Interface Materials With Polydisperse Fillers: Packing Algorithm and Effective Properties
Publikováno v:
ASME 2018 International Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Microsystems.
Thermal interface materials (TIMs), which transmit heat from semiconductor chips, are indispensable in today’s microelectronic devices. Designing superior TIMs for increasingly demanding integration requirements, especially for server-level hardwar
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fa255da3c0e980a23d7707a3da7f3d70
https://doi.org/10.1115/ipack2018-8337
https://doi.org/10.1115/ipack2018-8337
Autor:
Tsuyoshi Furukawa, Anuja De Silva, Luciana Meli, Jing Guo, Dominik Metzler, Indira Seshadri, Ramakrishnan Ayothi, Yann Mignot, Nelson Felix, Dan Corliss, Abraham Arceo de la Pena, Lovejeet Singh, Yongan Xu
Publikováno v:
Advances in Patterning Materials and Processes XXXV.
Current EUV lithography pushes photoresist thickness reduction to sub-30 nm in order to meet resolution targets and mitigate pattern collapse. In order to maintain the etch budgets in hard mask open, the adhesion layer in between resist and hard mask
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::41cbf5c74590ace109995f88f7b1f25c
https://doi.org/10.1117/12.2297113
https://doi.org/10.1117/12.2297113
Autor:
Oleg Gluschenkov, Zuoguang Liu, Chengyu Niu, Andreas Knorr, Tenko Yamashita, Jay W. Strane, Mukesh Khare, Gen Tsutsui, Chris M. Prindle, Abraham Arceo, Indira Seshadri, Bruce Miao, A. Petrescu, Stan D. Tsai, Curtis Durfee, Soon-Cheon Seo, Adra Carr, Jie Yang, Walter Kleemeier, Kisik Choi, F. Lie, W. Wang, Rama Divakaruni, Chanro Park, Mark Raymond, Heng Wu, Huiming Bu, Dechao Guo, Anuja DeSilva, George Yang, Dinesh Gupta, Muthumanickam Sankarapandian, Praneet Adusumilli, Sam Choi, Kerem Akarvardar
Publikováno v:
2017 IEEE International Electron Devices Meeting (IEDM).
In this study, a manufacturable CMOS dual solid phase epitaxy (SPE) process with pc < 2.2×10−9 Q-cm2 on both NFET and PFET is demonstrated on the hardware with 7nm ground rule. Contact resistivity reduction strategies of both the conventional appr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fafc4c9a45bd4b7e938db8bc086dead4
https://doi.org/10.1109/iedm.2017.8268440
https://doi.org/10.1109/iedm.2017.8268440