Zobrazeno 1 - 10
of 12
pro vyhledávání: '"Imran Wali"'
Publikováno v:
ICECS
Front-end designs of OS-powered SoCs are developed to be implemented on SRAM-based FPGAs, which can be used in low-cost space applications. In this work, we evaluate the impact of OS on the reliability of a RISC-V based SoC, against configuration mem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4da953d60e580a7e8af46931115ca1f
https://doi.org/10.1109/icecs49266.2020.9294858
https://doi.org/10.1109/icecs49266.2020.9294858
Autor:
Arnaud Virazel, Imran Wali, M. Sonza Reorda, Serge Pravossoudovitch, Patrick Girard, Alberto Bosio
Publikováno v:
Journal of Electronic Testing
Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. ⟨10.1007/s10836-016-5578-0⟩
Journal of Electronic Testing, Springer Verlag, 2016, 32 (2), pp.147-161. ⟨10.1007/s10836-016-5578-0⟩
International audience; Increasing vulnerability of transistors and interconnects due to scaling is continuously challenging the reliability of future microprocessors. Lifetime reliability is gaining attention over performance as a design factor even
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::65ae73dbb3a25e2eae159a1b764421ab
https://doi.org/10.1007/s10836-016-5578-0
https://doi.org/10.1007/s10836-016-5578-0
Publikováno v:
DASIP
For arithmetic circuits, Reduced-Precision Redundancy (RPR) is considered to be a viable alternative to Triple Modular Redundancy (TMR), as it offers significant power reduction. However, efficient implementation and assessment of hardware arithmetic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::dd6543a691c85a7bfdbf79b82fb547ef
https://doi.org/10.1109/dasip.2017.8122117
https://doi.org/10.1109/dasip.2017.8122117
Autor:
Imran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard, Mario Barbareschi, Alberto Bosio
Publikováno v:
3rd Workshop On Approximate Computing In conjunction with HiPEAC
WAPCO: Workshop On Approximate Computing
WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
HAL
WAPCO: Workshop On Approximate Computing
WAPCO: Workshop On Approximate Computing, Jan 2017, Stockholm, Sweden
HAL
International audience; In the recent years Approximate Computing (AC) has emerged as new paradigm for energy efficient IC design. It addresses the problem of maintaining reliability and thus coping with run-time errors exploiting an acceptable amoun
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::04680f4cad5ca540e3ef5c98e4df27da
https://hal-lirmm.ccsd.cnrs.fr/lirmm-02004418/document
https://hal-lirmm.ccsd.cnrs.fr/lirmm-02004418/document
Publikováno v:
21th IEEE European Test Symposium
ETS: European Test Symposium
ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩
Journal of Electronic Testing
Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩
ETS: European Test Symposium
ETS: European Test Symposium, May 2016, Amsterdam, Netherlands. ⟨10.1109/ETS.2016.7519296⟩
Journal of Electronic Testing
Journal of Electronic Testing, Springer Verlag, 2017, 33 (1), pp.25-36. ⟨10.1007/s10836-017-5640-6⟩
International audience; Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art reliability estimation methods makes
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::aaef00d3d1277e330139c7d4bd0b1801
http://hdl.handle.net/11583/2663521
http://hdl.handle.net/11583/2663521
Autor:
Mario Barbareschi, Marcello Traiola, Imran Wali, Patrick Girard, Alberto Bosio, Arnaud Virazel
Publikováno v:
DDECS
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. ⟨10.1109/DDECS.2017.7934574⟩
20th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems
DDECS: Design and Diagnostics of Electronic Circuits and Systems, Apr 2017, Dresden, Germany. ⟨10.1109/DDECS.2017.7934574⟩
International audience; In the recent years, Approximate Computing (AC) has emerged as a new paradigm for energy efficient design of Integrated Circuits (ICs). AC is based on the intuitive observation that, while performing exact computation requires
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9e3153da3da002cc7ce9260637c69f11
https://hdl.handle.net/11588/915813
https://hdl.handle.net/11588/915813
Publikováno v:
ETS
Selecting the ideal trade-off between reliability and cost associated with a fault tolerant architecture generally involves an extensive design space exploration. Employing state-of-the-art susceptibility estimation methods makes it unscalable with d
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::fae578f60b083924b66a4f618d99da04
http://hdl.handle.net/11583/2650514
http://hdl.handle.net/11583/2650514
Publikováno v:
7th International Conference on Advances in System Testing and Validation Lifecycle
VALID: Advances in System Testing and Validation Lifecycle
VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6
HAL
VALID: Advances in System Testing and Validation Lifecycle
VALID: Advances in System Testing and Validation Lifecycle, Nov 2015, Barcelone, Spain. pp.1-6
HAL
International audience; This paper provides a comparative study based on experiments performed on four similar fault-tolerant architectures intended to reduce errors caused due to faults in combinational logic parts of microelectronic circuits and sy
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=dedup_wf_001::98af9631ae10ddfb3da3e05865e7081a
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01354754/file/valid_2015_1_10_40053.pdf
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01354754/file/valid_2015_1_10_40053.pdf
Publikováno v:
IEEE 21st International Symposium on
Testing and Robust System Design
IOLTS: International
Testing Symposium
Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, ⟨10.1109/IOLTS.2015.7229838⟩
IOLTS
Testing and Robust System Design
IOLTS: International
Testing Symposium
Testing Symposium, Jul 2015, Halkidiki, Greece. pp.89-94, ⟨10.1109/IOLTS.2015.7229838⟩
IOLTS
International audience; Fault-tolerant architectures have been widely used in industry to prevent circuit reliability from becoming a bottleneck for the development of robust high-performance and low-power systems. One such solution is a Hybrid Fault
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::61bb94b8cd42fdd2b0e3e7c6fa4ffd66
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272735
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272735
Publikováno v:
20th European Test Symposium
ETS: European Test Symposium
ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138733⟩
ETS
ETS: European Test Symposium
ETS: European Test Symposium, May 2015, Cluj-Napoca, Romania. ⟨10.1109/ETS.2015.7138733⟩
ETS
International audience; Increasing vulnerability of transistors and interconnects due to CMOS technology scaling is continuously challenging the reliability of future electronic circuits and systems. Lifetime reliability is gaining attention over per
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eb420a622453fdb3bcf93f7dcfabdc49
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730
https://hal-lirmm.ccsd.cnrs.fr/lirmm-01272730