Zobrazeno 1 - 10
of 14
pro vyhledávání: '"Ilya Issenin"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 17:1343-1347
With advances in process technology, soft errors are becoming an increasingly critical design concern. Owing to their large area, high density, and low operating voltages, caches are worst hit by soft errors. Based on the observation that in multimed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ad4a2324ca5a46b258b5b886f5bdcde6
https://doi.org/10.1109/tvlsi.2008.2002427
https://doi.org/10.1109/tvlsi.2008.2002427
Publikováno v:
Scopus-Elsevier
Exploiting runtime memory access traces can be a complementary approach to compiler optimizations for the energy reduction in memory hierarchy. This is particularly important for emerging multimedia applications since they usually have input-sensitiv
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d3e60938dcb425b363acb50a12d8c82b
https://doi.org/10.1109/tcad.2009.2014002
https://doi.org/10.1109/tcad.2009.2014002
Publikováno v:
Scopus-Elsevier
Horizontally partitioned caches (HPCs) are a power-efficient architectural feature in which the processor maintains two or more data caches at the same level of hierarchy. HPCs help reduce cache pollution and thereby improve performance. Consequently
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::a5a3e2819c2ad588905e019c71572bd5
https://doi.org/10.1109/tcad.2009.2013275
https://doi.org/10.1109/tcad.2009.2013275
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:1439-1452
As technology advances, it becomes feasible to implement a large multiprocessor systems-on-chip (MPSoCs) to satisfy the increased performance demands of embedded applications. The increased complexity of systems leads to an increased power consumptio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::254eaadf2cd60692d6aeda9d6f504d29
https://doi.org/10.1109/tcad.2008.925781
https://doi.org/10.1109/tcad.2008.925781
Autor:
Ilya Issenin, Nikil Dutt
Publikováno v:
International Journal of Parallel Programming. 36:93-113
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d350952b3b50e455eb32f6dc8cf2b51e
https://doi.org/10.1007/s10766-007-0041-6
https://doi.org/10.1007/s10766-007-0041-6
Publikováno v:
LCTES
Embedded multimedia applications consist of regular and irregular memory access patterns. Particularly, irregular pattern are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (S
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c23f1f3f25b2060004e9bc110ea7a192
https://doi.org/10.1145/1375657.1375664
https://doi.org/10.1145/1375657.1375664
Autor:
Ilya Issenin, Nikil Dutt
Publikováno v:
DATE
In today's embedded applications a significant portion of energy is spent in the memory subsystem. Several approaches have been proposed to minimize this energy, including the use of scratch pad memories, with many based on static analysis of a progr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::bc7ac842e5b12158da12226bcb270693
http://arxiv.org/abs/0710.4640
http://arxiv.org/abs/0710.4640
Publikováno v:
CASES
Many embedded array-intensive applications have irregular access patterns that are not amenable to static analysis for extraction of access patterns, and thus prevent efficient use of a Scratch Pad Memory (SPM) hierarchy for performance and power imp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::880c07b4433a2f09ca13e48e0598d6e6
https://doi.org/10.1145/1289881.1289915
https://doi.org/10.1145/1289881.1289915
Autor:
Nikil Dutt, Ilya Issenin
Publikováno v:
IFIP – The International Federation for Information Processing ISBN: 9780387722573
IESS
IESS
NoCs present a possible communication infrastructure solution to deal with increased design complexity and shrinking time-to-market. The communication infrastructure is a significant source of energy consumption and many attempts at energy efficient
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f16380ebead4570d39cde159468afec6
https://doi.org/10.1007/978-0-387-72258-0_26
https://doi.org/10.1007/978-0-387-72258-0_26
Autor:
Ilya Issenin, Nikil Dutt
Publikováno v:
CODES+ISSS
The memory subsystem of a complex multiprocessor systems-on-chip (MPSoC) is an important contributor to the chip power consumption. The selection of memory architecture, as well as of communication architecture, both affect the power efficiency of th
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bb5b4424d6d22e3df3e88f4dfcf15bd
https://doi.org/10.1145/1176254.1176326
https://doi.org/10.1145/1176254.1176326