Zobrazeno 1 - 10
of 23
pro vyhledávání: '"Ilias Chlis"'
Publikováno v:
The Scientific World Journal, Vol 2014 (2014)
This paper reports comparative analyses of phase noise in Hartley, Colpitts, and common-source cross-coupled differential pair LC oscillator topologies in 28 nm CMOS technology. The impulse sensitivity function is used to carry out both qualitative a
Externí odkaz:
https://doaj.org/article/4a810de94c554bcb8b8c22c00d63f4ad
Autor:
Jae Wook Kim, Chuen-huei Adam Chou, Kee Hian Tan, Kun-Yung Ken Chang, Adebabay M. Bekele, Yohan Frans, H. Ahn, Ilias Chlis, Yipeng Wang, Arianne Roldan, David Mahashin, H.-W. Hung, Stanley Chen, Lei Zhou, Declan Carey, Hongtao Zhang, Ronan Casey, Jay Im, Ying Cao, Winson Lin, Kevin Zheng
Publikováno v:
IEEE Journal of Solid-State Circuits. 56:7-18
A 36-way time-interleaved 56-GS/s 7-bit ADC is designed to realize 112-Gb/s pulse-amplitude modulation (PAM-4) transceiver in a 7-nm FinFET CMOS. The receiver analog front-end stages and the ADC track-and-hold (T/H) buffers are implemented using inve
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d4a37bd68a77c15acd26014ce64d6ef
https://doi.org/10.1109/jssc.2020.3024261
https://doi.org/10.1109/jssc.2020.3024261
Autor:
Haritha Eachempatti, Kevin Geary, Neto Pedro W, Santiago Asuncion, Ben Griffin, Yohan Frans, Frantz Stephane Florent Ngankem Ngankem, Ilias Chlis, Jae Wook Kim, Asma Laraba, Kay Hearne, Marc Erett, Declan Carey, Ronan Casey, Hongtao Zhang, James Hudner
Publikováno v:
IEEE Solid-State Circuits Letters. 3:138-141
This letter describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-inte
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e694d8966cc7a487b9536105652d2130
https://doi.org/10.1109/lssc.2020.3007580
https://doi.org/10.1109/lssc.2020.3007580
Autor:
Yohan Frans, Hongtao Zhang, David Mahashin, Winson Lin, Yipeng Wang, Jay Im, Stanley Chen, Ken Chang, Adam Chou, Kevin Zheng, Hao-Wei Hung, Arianne Roldan, Ying Cao, Lei Zhou, Declan Carey, Ilias Chlis, Hong Ahn, Jae Wook Kim, Kee Hian Tan, Ronan Casey, Ade Bekele
Publikováno v:
ISSCC
Interest in 112Gb/s wireline transceivers targeting data center and communication applications has rapidly increased. PAM-4 signaling remains the dominant choice of modulation scheme due to its superior spectral efficiency [1-2]. This paper reports a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e96a0bf1319d2d9472a50d749861e697
https://doi.org/10.1109/isscc19947.2020.9063081
https://doi.org/10.1109/isscc19947.2020.9063081
Publikováno v:
Radio Science. 52:1117-1128
A 50 GHz cross-coupled differential-pair oscillator with a high-Q active inductor in the LC tank has been designed and fabricated in 65 nm bulk complementary metal-oxide semiconductor (CMOS) technology. The principle of operation is explained and a c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4bab4678e5234f0be7cac4ce63479f3a
https://doi.org/10.1002/2016rs006019
https://doi.org/10.1002/2016rs006019
Publikováno v:
International Journal of Circuit Theory and Applications. 45:1993-2016
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bf3ec16230d11b266c85c745e8b849a4
https://doi.org/10.1002/cta.2334
https://doi.org/10.1002/cta.2334
Publikováno v:
International Journal of Circuit Theory and Applications. 45:407-418
This paper reports a novel oscillator circuit topology based on a transformer-coupled π-network. As a case study, the proposed oscillator topology has been designed and studied for 60GHz applications in the frame of the emerging fifth generation wir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1f2854e4ee4baf1e7c38c71fe9b9c822
https://doi.org/10.1002/cta.2236
https://doi.org/10.1002/cta.2236
Publikováno v:
International Journal of Circuit Theory and Applications. 44:1697-1705
Summary This paper reports a phase noise analysis in a differential Armstrong oscillator circuit topology in CMOS technology. The analytical expressions of phase noise due to flicker and thermal noise sources are derived and validated by the results
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2960f8e5f8b5c16afe0193aa32a1da8a
https://doi.org/10.1002/cta.2187
https://doi.org/10.1002/cta.2187
Autor:
Hongtao Zhang, Declan Carey, David Mahashin, Neto Pedro W, Ken Chang, Asma Laraba, James Hudner, Yohan Frans, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Ilias Chlis, Chi Fung Poon, Kay Hearne, Marc Erett, Ronan Casey
Publikováno v:
VLSI Circuits
A 112Gb/s PAM4 wireline receiver testchip is implemented in 16nm FinFET. The receiver consists of continuous-time linear equalizers, a peaking capacitance buffer, and a 56GSa/s 64-way time-interleaved SAR ADC. The receiver achieves 2e-5 BER over a 20
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::967ab14878c9222ce248da2ea38f3449
https://doi.org/10.1109/vlsic.2018.8502436
https://doi.org/10.1109/vlsic.2018.8502436