Zobrazeno 1 - 10
of 15
pro vyhledávání: '"Ikki Nagaoka"'
Publikováno v:
Applied Physics Express, Vol 17, Iss 5, p 054501 (2024)
This study investigates the timing margin required to handle fluctuations and variations in superconductor single-flux-quantum gate-level-pipelined adders; a smaller timing margin would improve the clock frequencies of gate-level-pipelined circuits.
Externí odkaz:
https://doaj.org/article/e0b1f56f38304487ae7d4862b05ec30a
Publikováno v:
IEEE Transactions on Applied Superconductivity. 33:1-6
Autor:
Ikki Nagaoka, Ryota Kashima, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Taro Yamashita, Koji Inoue, Akira Fujimaki
Publikováno v:
IEEE Transactions on Applied Superconductivity. 33:1-11
Autor:
Ikki Nagaoka, Ryota Kashima, Koki Ishida, Masamitsu Tanaka, Taro Yamashita, Takatsugu Ono, Koji Inoue, Akira Fujimaki
Publikováno v:
IEEE Transactions on Applied Superconductivity. 33:1-8
Autor:
Ikki Nagaoka, Ryota Kashima, Tomoki Nakano, Masamitsu Tanaka, Taro Yamashita, Koji Inoue, Akira Fujimaki
Publikováno v:
2022 IEEE Asian Solid-State Circuits Conference (A-SSCC).
Autor:
Masamitsu Tanaka, Koji Inoue, Ikki Nagaoka, Takatsugu Ono, Taro Yamashita, Akira Fujimaki, Koki Ishida, Kyosuke Sano
Publikováno v:
IEEE Transactions on Applied Superconductivity. 31:1-5
A high-throughput 4 $\boldsymbol{\times }$ 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the del
Autor:
Manami Kuniyoshi, Kyosuke Sano, Masamitsu Tanaka, Ken Murase, Akira Fujimaki, Ikki Nagaoka, Taro Yamashita
Publikováno v:
IEEE Transactions on Applied Superconductivity. 31:1-5
In this study, the trade-off among power consumptions, operating frequencies, and error rates in low-power single-flux-quantum (SFQ) circuit is investigated. The power consumption of SFQ circuits can be reduced by the lowering critical currents ( $I_
Publikováno v:
IEEE Transactions on Applied Superconductivity. 31:1-6
We successfully demonstrated an 8-bit-wide, bit-parallel datapath composed of an arithmetic logic unit and register files for high-throughput oriented SFQ microprocessors based on a gate-level-pipeline structure. Achieving high-speed operation in the
Autor:
Ilkwon Byun, Junpyo Kim, Dongmoon Min, Ikki Nagaoka, Kosuke Fukumitsu, Iori Ishikawa, Teruo Tanimoto, Masamitsu Tanaka, Koji Inoue, Jangwoo Kim
Publikováno v:
Proceedings of the 49th Annual International Symposium on Computer Architecture.
Autor:
Koji Inoue, Masamitsu Tanaka, Satoshi Kawakami, Teruo Tanimoto, Ikki Nagaoka, Koki Ishida, Ilkwon Byun, Jangwoo Kim, Takatsugu Ono, Kosuke Fukumitsu
Publikováno v:
IEEE Micro. 41:19-26
The superconductor single-flux-quantum (SFQ) logic family has been recognized as a promising solution for the post-Moore era, thanks to the ultrafast and low-power switching characteristics of superconductor devices. Researchers have made tremendous