Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Ichiro Fujimori"'
Autor:
Sherif Abdalla, Ichiro Fujimori, Mark Chambers, Fazil Ahmad, Pin-En Su, Bo Shen, Greg Unruh, Amrutha Iyer
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:21-32
A phase-locked loop (PLL) architecture is proposed for improved efficiency of power and thermal management techniques in system-on-chips (SoCs). PLL architecture introduces two techniques: a dual-stage phase-acquisition loop filter that enables fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a18c0ff03e67911116e06b70d6fc819b
https://doi.org/10.1109/jssc.2016.2626338
https://doi.org/10.1109/jssc.2016.2626338
Autor:
Bo Zhang, Ichiro Fujimori, Siavash Fallahi, Hamid Hatamkhani, Kangmin Hu, Mohammed Abdul-Latif, Karapet Khanoyan, Haitao Tong, Kambiz Vakilian, Anthony Brewster
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:3089-3100
This paper presents a power- and area-efficient multistandard serial link transceiver designed for backplane application rates of up to 28 Gb/s, such as OIF CEI-25G, CEI-28G, and IEEE 802.3bj 100G-KR4. The receiver features a continuous-time linear e
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ba917c1d8252f27d4289bc4e61df3b2
https://doi.org/10.1109/jssc.2015.2475180
https://doi.org/10.1109/jssc.2015.2475180
Autor:
Yan Ge, Ichiro Fujimori, Chang-Hyeon Lee, Greg Unruh, Mark Chambers, Hendra Kwantono, Lindel Kabalican
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:856-866
A fractional-N LC-PLL in 28 nm CMOS that uses vertical layout integration techniques to achieve area reduction without performance penalties is proposed. The design utilizes multi-metal layers to vertically integrate dual interposed inductors on top
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e7fcf58821a96c6e9c841dad938f0d89
https://doi.org/10.1109/jssc.2014.2371136
https://doi.org/10.1109/jssc.2014.2371136
Publikováno v:
ISSCC
With the explosive data growth due to HD video content, IoT, and the rapid shift from enterprise to cloud computing, Mega Data Centers have become an essential part of the global network infrastructure. Despite their massive scale, Data Center archit
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::62be61cfc8009bb15ed4f6bcd9aa9c47
https://doi.org/10.1109/isscc.2017.7870483
https://doi.org/10.1109/isscc.2017.7870483
Autor:
Ichiro Fujimori, Pavan Hanumolu
Publikováno v:
ISSCC
This Evening Session is not about circuits or chip architectures; rather it is a technical session on economics driving the semiconductor industry. Business leaders (CEOs, CFOs, VCs, Investors) use very sophisticated financial engineering and analysi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::17d54380ef058be6f91b037ca49539d3
https://doi.org/10.1109/isscc.2017.7870488
https://doi.org/10.1109/isscc.2017.7870488
Autor:
Greg Unruh, Pin-En Su, Sherif Abdalla, Bo Shen, Fazil Ahmad, Ichiro Fujimori, Mark Chambers, Amrutha Iyer
Publikováno v:
ISSCC
Today's multicore processors and complex multimedia SoCs incorporate power management techniques such as dynamic frequency scaling (DFS), which dynamically changes operating frequencies, and dynamic core-count scaling (DCCS), which rapidly power cycl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5bc20f8272126b89618de4dc8e8cf7d2
https://doi.org/10.1109/isscc.2016.7418038
https://doi.org/10.1109/isscc.2016.7418038
Autor:
Martin Brox, Ichiro Fujimori, Pavan Kumar Hanumolu, Hideyuki Nosaka, Elad Alon, Gerritt den Besten
Publikováno v:
ISSCC
Ubiquitous connectivity within devices ranging from miniature sensors to racks for cloud datacenters is critical to enabling the “Internet of Everything”. Industry predictions suggest that the number of IoE devices may reach 200 billion by 2020,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::90a196b2167040a8fd6d66cec79eba40
https://doi.org/10.1109/isscc.2016.7418124
https://doi.org/10.1109/isscc.2016.7418124
Autor:
Delong Cui, Ichiro Fujimori, Wei Zhang, Adesh Garg, Ullas Singh, Bo Zhang, Jun Cao, Bharath Raghavan, Anand Vasani, Afshin Momtaz, Namik Kocaman, Deyi Pi, Hui Pan
Publikováno v:
IEEE Journal of Solid-State Circuits. 45:1172-1185
This paper presents the design of an analog-front-end (AFE) integrated into a DSP-based transceiver for both serial 10 Gbps KR-backplane and long-reach-multimode-fiber (LRM) applications. The receiver consists of a programmable gain amplifier (PGA) a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b0564f9ca861236edf6bdf54977a0fa2
https://doi.org/10.1109/jssc.2010.2047473
https://doi.org/10.1109/jssc.2010.2047473
Publikováno v:
IEEE Journal of Solid-State Circuits. 42:872-880
A 10 Gb/s receiver, containing an adaptive equalizer, a clock and data recovery, and a de-multiplexer, is implemented in 0.13-mum CMOS. The chip is intended for long-haul optical fiber links where chromatic and polarization mode dispersions are reach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d31874a2295850f3bf833e43d95b7f53
https://doi.org/10.1109/jssc.2007.892166
https://doi.org/10.1109/jssc.2007.892166
Publikováno v:
ISSCC
Time-interleaved ADCs have become critical components in high-speed wireline and wireless communication systems. This forum will deliver a comprehensive treatment of state-of-the art design techniques for high-speed interleaved ADCs. Topics include t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::67525d1e93dd92f61a8d9bb6adbf05ce
https://doi.org/10.1109/isscc.2015.7063142
https://doi.org/10.1109/isscc.2015.7063142