Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Ian Zhuang"'
Autor:
Jaeduk Han, Jay Im, Sen Lin, Ronan Casey, Ken Chang, Scott McLeod, Tim Cronin, Chuen-huei Adam Chou, Ian Zhuang, Parag Upadhyaya, Lei Zhou, Kevin Geary, Geoff Zhang, Arianne Roldan, Yohan Frans, Stanley Chen, Dave Freitas
Publikováno v:
IEEE Journal of Solid-State Circuits. 52:3486-3502
A 40–56 Gb/s PAM-4 receiver with ten-tap decision-feedback equalization (DFE) targeting chip-to-module and board-to-board cable interconnects is designed in 16-nm FinFET. The design implements direct feedback of the first post-cursor (h1) DFE tap t
Autor:
David Mahashin, Tim Cronin, Adebabay M. Bekele, Stanley Chen, Hongyuan Zhao, Ian Zhuang, Parag Upadhyaya, Adam Chou, Winson Lin, Kee Hian Tan, Dave Freitas, Lei Zhou, Kok Lim Chan, Yohan Frans, Jay Im, Ken Chang, Didem Turker
Publikováno v:
VLSI Circuits
A 28Gb/s NRZ wireline transceiver is implemented in 7nm FinFET. A transformer-based LC-PLL sends a single-phase differential clock to the voltage-mode transmitter and the receiver. Local multi-phase clocks are generated in each TX/RX lane to support
Autor:
Jaewook Shin, Stanley Chen, Lei Zhou, Jinyung Namkoong, Yohan Frans, Mayank Raj, Didem Turkur Melek, Jay Im, Ken Chang, Ian Zhuang
Publikováno v:
ISSCC
As ever-increasing bandwidth demand pushes wireline transceiver data-rates beyond 25Gb/s, the clocking solution for multi-protocol support over a wide range of data-rates becomes a key design challenge. In [1], an injection-locked multi-phase clock g
Autor:
Scott McLeod, Jay Im, Ken Chang, Ronan Casey, Sen Lin, Kevin Geary, Lei Zhou, Yohan Frans, Geoff Zhang, Dave Freitas, Ian Zhuang, Parag Upadhyaya, Adam Chou, Arianne Roldan, Tim Cronin, Jaeduk Han, Stanley Chen
Publikováno v:
ISSCC
The increasing bandwidth demand in data centers and telecommunication infrastructures had prompted new electrical interface standards capable of operating up to 56Gb/s per-lane. The CEI-56G-VSR-PAM4 standard [1] defines PAM-4 signaling at 56Gb/s targ