Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Ian Broster"'
Autor:
Chris Bryan, Florian Schanda, Martin Brain, Francisco Javier Guzman Jimenez, Simon Daniel, Daniel Kroening, Ian Broster, Youcheng Sun, Andrew Hawthorn, Thomas Wilson
Publikováno v:
ICECCS
Queen's University Belfast-PURE
Queen's University Belfast-PURE
We propose and demonstrate a method for the reduction of testing effort in safety-critical software development using DO-178 guidance. We achieve this through the application of Bounded Model Checking (BMC) to formal low-level requirements, in order
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d65f2331b5fa03f9ff89443e356fcf3a
https://ora.ox.ac.uk/objects/uuid:7db821b2-e57d-4a3e-88c3-5fae9d4f4bbd
https://ora.ox.ac.uk/objects/uuid:7db821b2-e57d-4a3e-88c3-5fae9d4f4bbd
Autor:
Mikel Fernandez, Carles Hernandez, Paulo Machado, Ian Broster, Jaume Abella, David Corrales Morales, Leonidas Kosmidis, Eduardo Quinones, Francisco J. Cazorla, Luca Fossati, Alen Bardizbanyan
Publikováno v:
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
DATE
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
DATE
Timing Verification is a fundamental step in real-time embedded systems, with measurement-based timing analysis (MBTA) being the most common approach used to that end. We present a Space case study on a real platform that has been modified to support
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::4f7101314c94b56a4a27718c641826cb
https://hdl.handle.net/2117/104524
https://hdl.handle.net/2117/104524
Autor:
Fabrice Cros, Carles Hernandez, Mikel Fernandez, Franck Wartel, Leonidas Kosmidis, Ian Broster, Cristian Maxim, Francisco J. Cazorla, Irune Aguirre, Benoit Triquet, Jan Andersson, Tullio Vardanega, Mladen Slijepcevic, Francis Vatrinet, Adriana Gogonel, Andrea Gianarro, Glenn Ashley Farrall, Liliana Cucu, David Corrales Morales, Mikel Azkarate-Askasua, Eduardo Quinones, Jaume Abella, Iain Bate, Code Lo, Philippa Conmy, Enrico Mezzetti, Walid Talaboulma
Publikováno v:
2016 Euromicro Conference on Digital System Design
2016 Euromicro Conference on Digital System Design, Aug 2016, Limassol, France. ⟨10.1109/DSD.2016.22⟩
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
DSD
2016 Euromicro Conference on Digital System Design, Aug 2016, Limassol, France. ⟨10.1109/DSD.2016.22⟩
Recercat. Dipósit de la Recerca de Catalunya
instname
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
DSD
The use of increasingly complex hardware and software platforms in response to the ever rising performance demands of modern real-time systems complicates the verification and validation of their timing behaviour, which form a time-and-effort-intensi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::886f143772e892a23dfa9bf5125e3a59
https://hdl.handle.net/2117/93003
https://hdl.handle.net/2117/93003
Autor:
Andrea Gianarro, Leonidas Kosmidis, Jaume Abella, Ian Broster, Carles Hernandez, Francisco J. Cazorla, Tullio Vardanega, Eduardo Quinones
Publikováno v:
UPCommons. Portal del coneixement obert de la UPC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Digital.CSIC. Repositorio Institucional del CSIC
Universitat Politècnica de Catalunya (UPC)
Recercat. Dipósit de la Recerca de Catalunya
instname
Digital.CSIC. Repositorio Institucional del CSIC
The pressing market demand for competitive performance/cost ratios compels Critical Real-Time Embedded Systems industry to employ feature-rich hardware. The ensuing rise in hardware complexity however makes worst-case execution time (WCET) analysis o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::28bea35fd5b1c406c737b27fd750a9cd
Autor:
Jörg Mische, Hugues Cassé, Florian Kluge, Sebastian Kehr, Sascha Uhrig, Francisco J. Cazorla, Armelle Bonenfant, Bert Böddeker, Lucie Matusova, Jaume Abella, Christian Bradatsch, Milos Panic, Zai Jian Jia Li, Mike Gerdes, Theo Ungerer, Carles Hernandez, Christine Rochange, Martin Frieb, Eduardo Quinones, David George, Zlatko Petrov, Ian Broster, Pavel Zaykov, Ralf Jahr, Hans Regler, Pascal Sainrat, Arthur Pyka, Haluk Ozaktas, Andreas Hugl, Alexander Stegmeier, Nick Lay, Mathias Rohde
Publikováno v:
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (3), ⟨10.1145/2910589⟩
ACM Transactions on Embedded Computing Systems (TECS), ACM, 2016, 15 (3), ⟨10.1145/2910589⟩
International audience; The EC project parMERASA (Multicore Execution of Parallelized Hard Real-Time Applications Supporting Analyzability) investigated timing-analyzable parallel hard real-time applications running on a predictable multicore process
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::eba8fcccc1a4e0b12f79e039b2c091a7
https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/54088
https://opus.bibliothek.uni-augsburg.de/opus4/frontdoor/index/index/docId/54088
Publikováno v:
Real-Time Systems. 30:55-81
This paper discusses aspects of dependability of real-time communication. In particular, we consider timing behaviour under fault conditions for Controller Area Network (CAN) and the extension Time-triggered CAN (TTCAN) based on a time-driven schedul
Autor:
Ian Broster, Francisco J. Cazorla, Tullio Vardanega, Leonidas Kosmidis, Eduardo Quinones, Jaume Abella
Publikováno v:
DSD
Critical Real-Time Embedded Systems (CRTES) industry needs increasingly complex hardware to attain the performance/cost ratio required to keep competitive edge in the market. Worst-case execution time (WCET) analysis is central to CRTES development.
Autor:
Arthur Pyka, Haluk Ozaktas, Dave George, João Carlos Lopes Fernandes, Hugues Cassé, Florian Kluge, Milos Panic, Pavel Zaykov, Theo Ungerer, Armelle Bonenfant, Ralf Jahr, Bert Böddeker, Zlatko Petrov, Hans Regler, Mike Gerdes, Andreas Hugl, Christian Bradatsch, Sascha Uhrig, Jaume Abella, Mathias Rohde, Sebastian Kehr, Francisco J. Cazorla, Ian Broster, Nick Lay, Christine Rochange, Pascal Sainrat, Eduardo Quinones, Jörg Mische
Publikováno v:
DSD
Proceedings of DSD 2013
16th Euromicro Conference on Digital System Design (DSD 2013)
16th Euromicro Conference on Digital System Design (DSD 2013), Sep 2013, Santander, Spain. pp. 363-370
Proceedings of DSD 2013
16th Euromicro Conference on Digital System Design (DSD 2013)
16th Euromicro Conference on Digital System Design (DSD 2013), Sep 2013, Santander, Spain. pp. 363-370
International audience; Engineers who design hard real-time embedded systems express a need for several times the performance available today while keeping safety as major criterion. A breakthrough in performance is expected by parallelizing hard rea
Publikováno v:
International Journal on Software Tools for Technology Transfer
Observing the timing properties of actual software provides information not derivable from pure modelling of the hardware, software and test data. Equally, modelling provides worst-case timing values that cannot be realistically determined from only