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pro vyhledávání: '"I.M. Bell"'
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Publikováno v:
Analog Integrated Circuits and Signal Processing. 82:265-283
With the help of automated model generation (AMG), high level modeling (HLM) of analog circuits is able to provide useful speedup and acceptable accuracy compared with standard SPICE-level circuit simulation. Unfortunately, this is not the case for h
Akademický článek
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Publikováno v:
Journal of Electronic Testing. 29:861-877
It is known that automated model generation (AMG) techniques for linear systems are sufficiently mature to handle linear systems during high level modeling (HLM). Other AMG techniques have been developed for various levels of nonlinear behavior and t
Autor:
Michael J. Bowes, Stephen J. Haswell, M. Loewenthal, Andrew J. Wade, Gillian M. Greenway, S. J. Halliday, E. Gozzard, H. J. Jarvie, I.M. Bell, Etienne Joly, Colin Neal, Ahmed Fallatah, Jonathan Newman, Elizabeth J. Palmer-Felgate, Richard J. Williams, Richard Skeffington
Publikováno v:
Hydrology and Earth System Sciences, Vol 16, Iss 11, Pp 4323-4342 (2012)
This paper introduces new insights into the hydrochemical functioning of lowland river systems using field-based spectrophotometric and electrode technologies. The streamwater concentrations of nitrogen species and phosphorus fractions were measured
Autor:
I.M. Bell, Thomas O. Myers
Publikováno v:
Journal of Electronic Testing. 27:363-373
In this paper we introduce a Microfluidic Fault Simulator, MFS, which uses a novel method of fault modeling and injection, the Fault Block, a generic and low abstraction fault modeling technique. This technique has been utilized over a wide range of
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:1140-1145
High-level modeling for operational amplifiers (opamps) has been previously carried out successfully using models generated by published automated model generation approaches. Furthermore, high-level fault modeling (HLFM) has been shown to work reaso
Publikováno v:
Journal of Systems Architecture, 53(5-6), 253-262. Elsevier
This paper presents a scalable and partitionable asynchronous bus arbiter for use with chip multiprocessors and its corresponding pre-layout simulation results using VHDL. The arbiter exploits the advantage of a concurrency control instruction (Brk)
Publikováno v:
International Journal of Parallel Programming, 34(4), 343-381. Springer New York
Chip multiprocessors (CMPs) hold great promise for achieving scalability in future systems. Microthreaded CMPs add a means of exploiting legacy code in such systems. Using this model, compilers generate parametric concurrency from sequential source c