Zobrazeno 1 - 10
of 12
pro vyhledávání: '"I. Vivek Anand"'
Publikováno v:
Silicon. 14:4589-4600
The influence of trap carriers at the Si-SiO2 interface near the source channel junction is analysed in this paper. The drain current is computed using the analytical model and it is expanded for constructing the SiO2/HfO2 cylindrical gate tunnel FET
Publikováno v:
Materials Today: Proceedings. 45:4026-4035
Three different work functions are taken in this paper for investigating a hetero-junction tri gate tunnel FET and it is simulated using TCAD. The proposed device employs hetero-junction structure that exhibits lesser band-gap between source and intr
Publikováno v:
Journal of Computational Electronics. 19:1450-1462
Analytical modeling of a dual-material asymmetric heterodielectric-gate tunnel field-effect transistor (FET) is carried out based on the Poisson equation and parabolic approximation techniques. An asymmetric gate with two materials having different w
Publikováno v:
Journal of Nano Research. 62:47-58
Analytical modelling for a tri material cylindrical gate tunnel FET is developed in this paper. Poisson equation and parabolic approximation technique are employed to develop the analytical model of the proposed device. Inorder to eliminate the influ
Publikováno v:
Journal of Pharmaceutical Negative Results; 2022 Special Issue, Vol. 13, p362-371, 10p
Autor:
K. Mari Priyadharshini, A. Karthihaa, L. Sivasankari, S. Karthika, T. S. Arun Samuel, I. Vivek Anand
Publikováno v:
INTERNATIONAL VIRTUAL CONFERENCE ON RECENT MATERIALS AND ENGINEERING APPLICATIONS FOR SUSTAINABLE ENVIRONMENT (ICRMESE2020).
Development of high performance embedded platforms concentrates on handling huge computational requirements of complex algorithm. For high ended applications, execution of the processor will shift agreeing to the code being executed. Consequent enlig
Publikováno v:
Superlattices and Microstructures. 162:107099
In semiconductor industry, at nanoscale dimensions, numerous field effect devices have been proposed and investigated for further improvement in performance of low power circuit and system. In the present research report, a novel low power FET device
Autor:
A. Kamaraj, I. Vivek Anand
Publikováno v:
International Conference on Information Communication and Embedded Systems (ICICES2014).
The circuits like Logic gates, Adders, Multipliers are the basic building block of the digital circuits. These combinational circuits can be designed by using the concepts of the reversible logic. The reversible logic is either a physically reversibl
Conference
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Akademický článek
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