Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Hyung-Ock Kim"'
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 18:505-509
Power-gating has been widely used to reduce subthreshold leakage current. However, the extent of leakage saving through power-gating diminishes with technology scaling due to gate leakage of data-retention circuit elements. Furthermore, power-gating
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b02f123c30d302286237555eb9954f90
https://doi.org/10.1109/tvlsi.2009.2012429
https://doi.org/10.1109/tvlsi.2009.2012429
Autor:
Bong Hyun Lee, Hyun-Woo Kim, Hyung-Ock Kim, Seung Ho Hwang, Hyo-sig Won, Seung Chul Lee, Jung Yon Choi, Kyu-Myung Choi
Publikováno v:
JSTS:Journal of Semiconductor Technology and Science. 9:240-248
Moore's law has driven silicon technology scale down aggressively, and it results in significant increase of leakage current on nano-meter scale CMOS. Especially, in mobile devices, leakage current has been one of designers' main concerns, and thus m
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2bd3a4d04e0f27dbb4a13446b5cdf359
https://doi.org/10.5573/jsts.2009.9.4.240
https://doi.org/10.5573/jsts.2009.9.4.240
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 28:327-339
Zigzag power gating (ZPG) can overcome the long wake-up delay of standard power gating, but its requirement for both nMOS and pMOS current switches, in a zigzag pattern, requires complicated power networks, limiting application to custom designs. We
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e4150c941dbfaf965db5bee5536c3dbc
https://doi.org/10.1109/tcad.2009.2012532
https://doi.org/10.1109/tcad.2009.2012532
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 15:758-766
Power gating has been widely used to reduce subthreshold leakage. However, the efficiency of power gating degrades very fast with technology scaling, which we demonstrate by experiment. This is due to the gate leakage of circuits specific to power ga
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5e4778107ad2e390b4100aa0623f7b30
https://doi.org/10.1109/tvlsi.2007.899228
https://doi.org/10.1109/tvlsi.2007.899228
Publikováno v:
ISPD
We propose a new coarse-grained structural placement methodology tightly coupled with logic synthesis to exploit inherent structure of a synthesized parallel multiplier. The proposed method takes advantage of both benefits of logic optimizations and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::48dc4f8ff68e3a68320452515026de1a
https://doi.org/10.1145/2717764.2717775
https://doi.org/10.1145/2717764.2717775
Autor:
Jung Yun Choi, Bernd Becker, Kee Sup Kim, Kyung-Tae Do, Young Moon Kim, Hyung-Ock Kim, Matthias Sauer, Jun Seomun, Subhasish Mitra
Publikováno v:
CICC
Using 28nm test chips, we derive signatures for early-life failures (ELF) in both high-K/metal-gate transistors and ultra low-K inter-metal dielectrics. We also demonstrate that the derived ELF signatures can be successfully detected using a clock co
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9eecbd8a552946329fbda1913f9fbe31
https://doi.org/10.1109/cicc.2013.6658544
https://doi.org/10.1109/cicc.2013.6658544
Autor:
Jung Yun Choi, Bernd Becker, Young Moon Kim, Kyung-Tae Do, Matthias Sauer, Subhasish Mitra, Jun Seomun, Kee Sup Kim, Hyung-Ock Kim
Publikováno v:
ITC
Early-life failures (ELF) result from weak chips that may pass manufacturing tests but fail early in the field, much earlier than expected product lifetime. Recent experimental studies over a range of technologies have demonstrated that ELF defects r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2fc9efee9e1d6299c9ac79a5fac02a36
https://doi.org/10.1109/test.2013.6651925
https://doi.org/10.1109/test.2013.6651925
Autor:
Jun Seomun, Chungki Oh, Kee Sup Kim, Wook Kim, Hyo-sig Won, Jae-Han Jeon, Kyung-Tae Do, Hyung-Ock Kim
Publikováno v:
ISOCC
Thermal management, which dynamically throttles frequency and voltage, is de facto standard in high performance mobile SoC to sustain device surface temperature under specific level; and throttling must accompany with computation slowdown. To minimiz
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f7cb7ae9e02b5ac9ed186afb723b016
https://doi.org/10.1109/isocc.2012.6407061
https://doi.org/10.1109/isocc.2012.6407061
Publikováno v:
ASP-DAC
Power gating has been widely used to reduce subthreshold leakage. However, its efficiency degrades very fast with technology scaling due to the gate leakage of circuits specific to power gating, such as storage elements and output interface circuits
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bda66ebde2c6a4e0655d72af49f47058
https://doi.org/10.1109/aspdac.2007.358061
https://doi.org/10.1109/aspdac.2007.358061
Autor:
Youngsoo Shin, Hyung-Ock Kim
Publikováno v:
ASP-DAC
Power gating is widely accepted as an efficient way to suppress subthreshold leakage current. Yet, it suffers from gate leakage current, which grows very fast with scaling down of gate oxide. We try to understand the sources of leakage current in pow
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9c92ecc017154248f0dc824a49a2d727
https://doi.org/10.1145/1118299.1118434
https://doi.org/10.1145/1118299.1118434