Zobrazeno 1 - 4
of 4
pro vyhledávání: '"Hyung Gyun Yang"'
Autor:
Yong-Jun Lee, Hyung Gyun Yang, Jong-Won Kim, Hakbeom Jang, Jangwoo Kim, Jinkyu Jeong, Jae W. Lee
Publikováno v:
ISCA
This paper introduces a tagless cache architecture for large in-package DRAM caches. The conventional die-stacked DRAM cache has both a TLB and a cache tag array, which are responsible for virtual-to-physical and physical-to-cache address translation
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9847a928a80abb860ac2c2251c215a8b
https://doi.org/10.1145/2749469.2750383
https://doi.org/10.1145/2749469.2750383
Autor:
Young Hoon Son, Seongil O, Hyung Gyun Yang, Jung Ho Ahn, Daejin Jung, Jae W. Lee, Jangwoo Kim, John Kim
Publikováno v:
SC
Through-Silicon Interposer (TSI) has recently been proposed to provide high memory bandwidth and improve energy efficiency of the main memory system. However, the impact of TSI on main memory system architecture has not been well explored. While TSI
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c9e3c961a6a3f9d439e3113e65f214d
https://doi.org/10.1109/sc.2014.91
https://doi.org/10.1109/sc.2014.91
Publikováno v:
2008 International SoC Design Conference.
Satisfying timing constraint is the most important issue in today's VLSI design. The recent increase of process variation, however, made it too difficult to predict the circuit timing accurately using traditional deterministic methods. Many statistic
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bca062d7c6063b7de4b6c8dbacecffdc
https://doi.org/10.1109/socdc.2008.4815715
https://doi.org/10.1109/socdc.2008.4815715
Publikováno v:
2010 International Conference on Electrical Engineering/Electronics Computer Telecommunications & Information Technology (ECTI-CON); 2010, p376-379, 4p