Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Hyochang Kim"'
Autor:
Yesin Ryu, Sung-Gi Ahn, Jae Hoon Lee, Jaewon Park, Yong Ki Kim, Hyochang Kim, Yeong Geol Song, Han-Won Cho, Sunghye Cho, Seung Ho Song, Haesuk Lee, Useung Shin, Jonghyun Ahn, Je-Min Ryu, Sukhan Lee, Kyoung-Hwan Lim, Jungyu Lee, Jeong Hoan Park, Jae-Seung Jeong, Sunghwan Joo, Dajung Cho, So Young Kim, Minsu Lee, Hyunho Kim, Minhwan Kim, Jae-San Kim, Jinah Kim, Hyun Gil Kang, Myung-Kyu Lee, Sung-Rae Kim, Young-Cheon Kwon, Young Yong Byun, Kijun Lee, Sangkil Park, Jaeyoun Youn, Myeong-O Kim, Kyomin Sohn, Sang-Joon Hwang, Jooyoung Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 58:1051-1061
Publikováno v:
International Journal of Human–Computer Interaction. :1-10
Autor:
Changsik Yoo, Hyochang Kim
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:1107-1117
A receiver for a three-lane 6-Gb/s/lane serial link has been developed in 28-nm CMOS technology. It incorporates an intrapair skew compensator (IPSC) and a three-tap decision feedback equalizer (DFE). The IPSC removes the IPS in analog front end by a
Publikováno v:
IEEE Transactions on Circuits and Systems II: Express Briefs. :1-1
Autor:
Hyochang Kim, Changsik Yoo
Publikováno v:
JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE. 18:509-517
Autor:
Hyochang Kim, Changsik Yoo
Publikováno v:
Analog Integrated Circuits and Signal Processing. 96:363-370
A four-lane 12-Gb/s per lane high-definition multimedia interface (HDMI) 2.1 transmitter is developed in 28-nm bulk CMOS process. To relieve the burden of the generation and distribution of clock, quarter-rate architecture is employed where the duty-
Publikováno v:
2018 IEEE 27th Conference on Electrical Performance of Electronic Packaging and Systems (EPEPS).
The simultaneous switching noise (SSN) and the electro-magnetic interference (EMI) of single-ended signaling are avoided by the proposed balanced single-ended signaling (BASES) technique. The BASES allows a wire to have three voltage levels and ensur
Publikováno v:
International Journal of Electronics Letters. 1:77-86
A clock and data recovery (CDR) circuit has been developed for a clock-forwarded 3.4-Gbps serial link. The loss of the signal channel is compensated by a linear equaliser whose output is applied to eight samplers which provides edge- and data-samples
Autor:
Jun-Gi Jo, Ook Kim, Kyuhwan Oh, Hyochang Kim, Jaewoo Park, Changsik Yoo, Woosang Han, Taekjun Ahn
Publikováno v:
ICCE
A system-on-chip (SoC) has been developed in a 130-nm CMOS technology that converts HDMI input to MHL output and allows a mobile handset to display its video contents on a large screen television (TV) or monitor. The functionalities of the SoC have b
Publikováno v:
IEICE Electronics Express. 14:20170497-20170497