Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Hyeong-Rak Lim"'
Autor:
Sang-Hyeon Kim, Seong-Kwang Kim, Jae-Phil Shim, Dae-Myeong Geum, Gunwu Ju, Han-Sung Kim, Hee-Jeong Lim, Hyeong-Rak Lim, Jae-Hoon Han, Subin Lee, Ho-Sung Kim, Pavlo Bidenko, Chang-Mo Kang, Dong-Seon Lee, Jin-Dong Song, Won Jun Choi, Hyung-Jun Kim
Publikováno v:
IEEE Journal of the Electron Devices Society, Vol 6, Pp 579-587 (2018)
Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order
Externí odkaz:
https://doaj.org/article/20293a3a75a24531bcbca730df0a2068
Autor:
Seong Kwang Kim, Hyeong-Rak Lim, Jaejoong Jeong, Seung Woo Lee, Joon Pyo Kim, Jaeyoung Jeong, Bong Ho Kim, Seung-Yeop Ahn, Youngkeun Park, Dae-Myoung Geum, Younghyun Kim, Yongku Baek, Byung Jin Cho, Sang Hyeon Kim
Publikováno v:
2022 International Electron Devices Meeting (IEDM).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::64b84f597aa75cdf2c82279eedcd4ff4
https://doi.org/10.1109/iedm45625.2022.10019551
https://doi.org/10.1109/iedm45625.2022.10019551
Autor:
Dae-Myeong Geum, Won Jun Choi, Jaeyong Jeong, Hyeong-Rak Lim, Sanghyeon Kim, Seong Kwang Kim, Hyo-Jin Kim, Juhyuk Park, Jae-Hoon Han
Publikováno v:
IEEE Electron Device Letters. 42:800-803
We systematically investigated the wafer- bonded interfaces of p+GaAs/n+InGaAs and p+InGaAs/ n+InGaAs by using a circular transmission line method (CTLM) for the increased extraction accuracy. Based on the low-temperature bonding process at 50 °C, t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1cb16992c4bae1b710506c6eb8639bcc
https://doi.org/10.1109/led.2021.3076817
https://doi.org/10.1109/led.2021.3076817
Autor:
YeonJoo Jeong, Seong Kwang Kim, Jae-Hoon Han, Hyung-jun Kim, Dae-Myeong Geum, Hyeong-Rak Lim, Sanghyeon Kim
Publikováno v:
IEEE Electron Device Letters. 41:605-608
In this letter, we propose the photo-responsible synaptic devices by using stackable GaAs photodetectors (PDs) and Ge-on-insulator (Ge-OI) synaptic transistors for the future three-dimensional (3D) artificial vision sensors. The photo-responsible syn
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b5b17f057d94cc584785ffdfb7a1cefd
https://doi.org/10.1109/led.2020.2971321
https://doi.org/10.1109/led.2020.2971321
Autor:
Jae-Hoon Han, Yun-Joong Lee, Hyung-jun Kim, Byeong Kwon Ju, Sanghyeon Kim, Hansung Kim, Hyeong-Rak Lim, Dae-Myeong Geum, Seong Kwang Kim
Publikováno v:
IEEE Electron Device Letters. 40:1362-1365
In this letter, we have fabricated Ge-on-insulator (Ge-OI) junctionless (JL) n-MOSFETs via wafer bonding and epitaxial lift-off (ELO) techniques. We have evaluated the electrical characteristics of Ge-OI JL n-MOSFETs with different thickness of Ge ch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::989862a96e8ef4dc3a0ad998d1ad863f
https://doi.org/10.1109/led.2019.2931410
https://doi.org/10.1109/led.2019.2931410
Autor:
Pavlo Bidenko, Dae-Myeong Geum, Hyeong Rak Lim, Sanghyeon Kim, Yu Rim Jeon, Jae-Hoon Han, Hansung Kim, Chang Hwan Choi, YeonJoo Jeong, Hyung-jun Kim, Seong Kwang Kim, Yun Jung Lee
Publikováno v:
ACS applied materialsinterfaces. 12(6)
Although they have attracted enormous attention in recent years, software-based and two-dimensional hardware-based artificial neural networks (ANNs) may consume a great deal of power. Because there will be numerous data transmissions through a long i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::353cdfc67e9a0d3bc74d77e4a9b59eab
https://pubmed.ncbi.nlm.nih.gov/31939649
https://pubmed.ncbi.nlm.nih.gov/31939649
Autor:
Jae-Phil Shim, Sanghyeon Kim, Hyeong-Rak Lim, Hansung Kim, Hyung-jun Kim, Seong Kwang Kim, Jae-Hoon Han, Gun Wu Ju
Publikováno v:
IEEE Transactions on Electron Devices. 65:1253-1257
In this brief, we fabricated Ge (110)-on-insulator (-OI) structures on Si substrates via wafer bonding and epitaxial lift-off (ELO) process using Ge layer grown on GaAs for low-temperature layer stacking toward monolithic 3-D integration. We also sys
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::81eacdcfdb1bf045a302dc26ecf3a951
https://doi.org/10.1109/ted.2018.2793285
https://doi.org/10.1109/ted.2018.2793285
Autor:
Dae-Myeong Geum, Won Jun Choi, Hosung Kim, Chang-Mo Kang, Hyung-jun Kim, Hyeong-Rak Lim, Jae-Phil Shim, Jin Dong Song, Jae-Hoon Han, Dong-Seon Lee, Seongkwang Kim, Sanghyeon Kim, Hansung Kim, Subin Lee, Gun Wu Ju, Heejeong Lim, Pavlo Bidenko
Publikováno v:
IEEE Journal of the Electron Devices Society. 6:579-587
Monolithic 3-D integration has emerged as a promising technological solution for traditional transistor scaling limitations and interconnection bottleneck. The challenge we must overcome is a processing temperature limit for top side devices in order
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c0cf0102e447c842aedf6ef3e46f56a
https://doi.org/10.1109/jeds.2018.2802840
https://doi.org/10.1109/jeds.2018.2802840
Autor:
Won Jun Choi, Chang-Mo Kang, Hee Jung Lim, Hyung-jun Kim, Hyeong Rak Lim, Hansung Kim, Jae-Hoon Han, Gun Wu Ju, Dae-Myeong Geum, Seongkwang Kim, Dong-Seon Lee, Sanghyeon Kim, Jae-Phil Shim, Jin Dong Song
Publikováno v:
2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).
Monolithic 3D (M3D) integration has attracted lots of attentions to continue equivalent scaling by vertically stacking transistors [1]. It allows the reduction of the interconnect delay, resulting in reduction of the power consumption of the chip, wh
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::05397c0089d5f3a4febb240a8a07da05
https://doi.org/10.1109/s3s.2017.8309242
https://doi.org/10.1109/s3s.2017.8309242