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Publikováno v:
Journal of the Korean Society for Precision Engineering. 38:187-193
Publikováno v:
2020 IEEE 22nd Electronics Packaging Technology Conference (EPTC).
This paper presents that built-in stress of copper, FRP and solder-resist (SR) layers is critical to predict an IC package substrate's warpage at room temperature. The built-in stresses are 78MPa on copper, 16MPa on FR4 and 9MPa on SR through simple