Zobrazeno 1 - 10
of 13
pro vyhledávání: '"Hyang-ja Yang"'
Autor:
Jeong-Hyuk Choi, Jinho Ryu, Sang-Won Park, Myung-Hoon Choi, Hyang-ja Yang, Dae-Han Kim, Kye-Hyun Kyung, Donghun Kwak, Kitae Park, Dae-Seok Byeon, Jeong-Don Ihm, Jae-Hoon Jang, Moosung Kim, Kyung-Tae Kang, Doo-Sub Lee, Dongkyo Shim, Ji-Ho Cho, Wook-Ghee Hahn, You-Se Kim, Sang-Won Shim, Jae-Woo Im, Sang-Won Hwang, In-Mo Kim, Hyun-Jun Yoon, Doohyun Kim, Woopyo Jeong, Sang-Wan Nam, Seok-Min Yoon, HyunWook Park
Publikováno v:
IEEE Journal of Solid-State Circuits. 51:204-212
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as shorter tPROG, lower power consumption and higher endurance. For many years, every effort has been made to shrink die si
Autor:
Joonsoo Kwon, Hyun-Jun Yoon, Sung-Jun Kim, Dong-Kyu Youn, Jeung-Hwan Park, Kyungwa Yun, Doo-Sub Lee, Dongkyo Shim, HyunWook Park, Sang-Won Shim, Yang-Lo Ahn, Sang-Won Park, Doohyun Kim, Lee Kang-Bin, Hyung-Gon Kim, Kihwan Choi, Seung Hoon Shin, Jeong-Hyuk Choi, Taehyun Kim, Hyang-ja Yang, Ko Kuihan, Dae-Han Kim, Jinho Ryu, Woon-kyung Lee, Dae-Seok Byeon, Yoon-He Choi, Jinseon Yeon, Myong-Seok Kim, Han-soo Kim, Dong-Hyun Kim, Min-Su Kim, Donghun Kwak, Jinman Han, Won-Tae Kim, Kyung-Min Kang, Jae-Hoon Jang, Sang-Wan Nam, Kye-Hyun Kyung, Kitae Park, Moosung Kim, Pansuk Kwak, Myung-Hoon Choi, Du-Heon Song, Sungwhan Seo, Sung-Soo Lee
Publikováno v:
ISSCC
In the past few years, various 3D NAND Flash memories have been demonstrated, from device feasibility to chip implementation, to overcome scaling challenges in conventional planar NAND Flash [1-3]. The difficulties include shrinking the NAND cell and
Autor:
Kye-Hyun Kyung, Pansuk Kwak, Jeong-Hyuk Choi, Jinho Ryu, Young-Sun Min, Nayoung Choi, Hyung-Gon Kim, Dae-Seok Byeon, Doohyun Kim, Jeong-Don Ihm, Hyang-ja Yang, Yong Sung Cho, Jaedoeg Yu, Dong-Su Jang, Kyung-Tae Kang, In-Mo Kim, Bong-Kil Jung, Wandong Kim, Kyung-Min Kang, Chulbum Kim, Dongku Kang, Kitae Park, Sung-Yeon Lee, Moosung Kim, Lee Han-Jun, Woopyo Jeong, An-Soo Park, Jae-Ick Son, Doo-gon Kim, Doo-Sub Lee
Publikováno v:
ISSCC
Today's explosive demand for data transfer is accelerating the development of non-volatile memory with even larger capacity and cheaper cost. Since the introduction of 3D technology in 2014 [1], V-NAND is believed to be a successful alternative to pl
Autor:
Dae-Seok Byeon, Kyung-Hwa Kang, Yongsu Choi, Jeon Hongsoo, Hyung-Gon Kim, Minseok Kim, Jeong-Don Ihm, Seon-Kyoo Lee, Kye-Hyun Kyung, Sungwhan Seo, Sung-Min Joe, Jin-Yub Lee, Su-Chang Jeon, Kitae Park, Byung-Hoon Jeong, HyunWook Park, Moosung Kim, Kim Su-Yong, Sung-Won Yun, Sangbum Yun, Young-Min Kim, Park Jiyoon, Hyang-ja Yang, Jong-Hoon Lee, Yong-Sik Yim, Sungkyu Jo, Byung-Kyu Cho, Hyejin Yim, Makoto Hirano, Jonghoon Park, Tae-eun Kim, Deok-kyun Woo, Lee Kang-Bin, Chan-Ho Kim, Hoosung Kim, Jongyeol Park, Jung-no Im, Yang-Lo Ahn, Seung-jae Lee, Jeong-Hyuk Choi, Park Il-Han, Minsu Kim, Jin-Tae Kim, Dooho Cho, Ho-Kil Lee
Publikováno v:
ISSCC
NAND flash memory is widely used as a cost-effective storage with high performance [1–2]. This paper presents a 128Gb multi-level cell (MLC) NAND flash memory with a 150 cells/string structure in 14nm CMOS that can be used as a cost-effective stora
Autor:
Yong-Ki Cho, Dong-Min Kim, Seung-Jun Bae, Young-Sik Kim, Hyang-ja Yang, Sang-hyup Kwak, Beom-Sig Cho, Jae-Young Lee, Tae-Young Oh, Hye-Ran Kim, Byeong-Cheol Kim, Cheol-Goo Park, Yun-Seok Yang, Jeong-Don Lim, Chang-Ho Shin, Seok-Won Hwang, Min-Sang Park, Sam-Young Bang, Ji-Hoon Lim, Young-Ryeol Choi, Joo Sun Choi, Jin-Kook Kim, Dae Hyun Kim, Young-Hyun Jun, Gil-Shin Moon, Kwang-Il Park, Young-Soo Sohn, Jae-Hyung Lee, Jin-Hyun Kim, Hyun-Joong Kim
Publikováno v:
ISSCC
In the development of 3D graphic systems for higher resolution and more realistic modeling and rendering, graphic memories also have been playing a critical role to offer the required high bandwidth. Currently, GDDR5 SDRAM's provide with 7Gbps per pi
Autor:
Hyun-Jin Kim, Kyeong-Tae Kang, Seung Hoon Shin, Chae-Hoon Kim, Kitae Park, Kye-Hyun Kyung, Jeong-Hyuk Choi, Daehoon Na, Hyung-Gon Kim, Ji-Yeon Shin, Seon-Kyoo Lee, Jeong-Don Lim, Devraj Matharampallil Rajagopal, Ki-Sung Kim, Dae-Seok Byeon, Sang-Tae Kim, Chan-Jin Park, Han-Sung Joo, Jin-Tae Kim, Sung-Hoon Kim, Jaehwan Kim, Lee Jangwoo, Man-Joong Lee, Joon-Ho Shin, Seungwoo Yu, Hyang-ja Yang, Jeong-Joon Park, Do-Kook Kim, Yong-Jin Kwon, Minjae Lee
Publikováno v:
ISSCC
NAND Flash-based solid-state drives (SSDs) have been adopted in enterprise storage applications that require high capacity and high-throughput performance. In recent years, a SATA interface supporting only up to 600MB/S throughput has hindered the ac
Autor:
Sang-Hyun Joo, Jae-Hoon Jang, Jeong-Hyuk Choi, HyunWook Park, Ohsuk Kwon, Jinho Ryu, Doo-Sub Lee, Dongkyo Shim, Donghun Kwak, Kye-Hyun Kyung, Myung-Hoon Choi, Ji-Sang Lee, Jeong-Don Ihm, Sang-Won Park, Ji-Ho Cho, Kyung-Tae Kang, Jae-Woo Im, Sung-Ho Choi, Moosung Kim, Ki-Tae Park, Wook-Ghee Hahn, Seok-Min Yoon, You-Se Kim, Woopyo Jeong, Sang-Wan Nam, Dae-Seok Byeon, Sang-Won Hwang, Hyang-ja Yang, Dae-Han Kim, Hyun-Jun Yoon, In-Mo Kim, Sang-Won Shim, Young-Sun Min, Doohyun Kim
Publikováno v:
ISSCC
Most memory-chip manufacturers keep trying to supply cost-effective storage devices with high-performance characteristics such as smaller tPROG, lower power consumption and longer endurance. For many years, every effort has been made to shrink die si
Autor:
Ki-Tae Park, Jin-man Han, Daehan Kim, Sangwan Nam, Kihwan Choi, Min-Su Kim, Pansuk Kwak, Doosub Lee, Yoon-He Choi, Kyung-Min Kang, Myung-Hoon Choi, Dong-Hun Kwak, Hyun-wook Park, Sang-won Shim, Hyun-Jun Yoon, Doohyun Kim, Sang-won Park, Kangbin Lee, Kuihan Ko, Dong-Kyo Shim, Yang-Lo Ahn, Jeunghwan Park, Jinho Ryu, Donghyun Kim, Kyungwa Yun, Joonsoo Kwon, Seunghoon Shin, Dongkyu Youn, Won-Tae Kim, Taehyun Kim, Sung-Jun Kim, Sungwhan Seo, Hyung-Gon Kim, Dae-Seok Byeon, Hyang-Ja Yang, Moosung Kim, Myong-Seok Kim, Jinseon Yeon, Jaehoon Jang, Han-Soo Kim, Woonkyung Lee, Duheon Song, Sungsoo Lee, Kye-Hyun Kyung, Jeong-Hyuk Choi
Publikováno v:
2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).
Autor:
Gil-Shin Moon, Jeong-Don Lim, Hyang-ja Yang, Seung-Jun Bae, Dae Hyun Kim, Hye-Ran Kim, Woo-Seop Kim, Byeong-Cheol Kim, Dong-seok Kang, Cheol-Goo Park, Yong-Ki Cho, Yong-Jae Shin, Yun-Seok Yang, Gong-Heom Han, Young-Soo Sohn, Chang-Ho Shin, Min-Sang Park, Si-Hong Kim, Joo Sun Choi, sunyoung park, Ho-Seok Seol, Kwang-Il Park, Sam-Young Bang, Tae-Young Oh, Young-Ryeol Choi, Su-Yeon Doo, Young-Hyun Jun, Sang-hyup Kwak, Young-Sik Kim
Publikováno v:
ISSCC
Most DRAM interfaces such as GDDR5 and DDR3 use parallel single-ended signaling due to pin-count restriction and backward compatibility. Notwithstanding poor signal and power integrity issues, GDDR5 speed reached beyond 5Gb/s in recent years by utili
Autor:
Hwan-Wook Park, Sang-hyup Kwak, Kwang-Il Park, Dong-Min Kim, sunyoung park, Jae-Young Lee, Young-Hyun Jun, Tae-Young Oh, Yoo-seok Yang, Su-Yeon Doo, Woo-Seop Kim, Jin-Il Lee, Seung-Jun Bae, Dae Hyun Kim, Hyang-ja Yang, Ki-Woong Yeom, Sam-Young Bang, Young-Soo Sohn, Joo Sun Choi, Young-Sik Kim
Publikováno v:
2010 Symposium on VLSI Circuits.
A 7Gb/s single ended transceiver with low jitter and ISI is implemented in 40nm DRAM process. DRAM optimized LC PLL achieves inductor Q of 3.86 and results in random jitter of 670fs rms. A clock tree regulator with closed loop replica path reduces lo