Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Hwanseok Yeo"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 54:2823-2832
A 2 $\times $ blind-oversampling, fractionally spaced equalizer (FSE) receiver is presented as an effective way to combine adaptive equalization and timing recovery in a single control loop. To additionally support plesiochronous clocking, the presen
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0f48e59e1681eb8e29988935fffc276d
https://doi.org/10.1109/jssc.2019.2919417
https://doi.org/10.1109/jssc.2019.2919417
Publikováno v:
A-SSCC
A 2× blind-oversampling, fractionally-spaced equalizer (FSE) receiver is presented as an effective way to combine adaptive equalization and infinite-range timing recovery. A FSE can perform equalization as well as timing adjustment via data-interpol
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::87b8deffe389b7873be7d68d076e4642
https://doi.org/10.1109/asscc.2018.8579286
https://doi.org/10.1109/asscc.2018.8579286
Publikováno v:
IEEE Journal of Solid-State Circuits. 49:1773-1784
A 9.2 GHz digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer function is presented. In other words, the closed-loop transfer function of the proposed digital PLL does not possess a closed-loop zero and the PLL achieves fast
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5682b74cef7999a24df23db85a582c3b
https://doi.org/10.1109/jssc.2014.2312412
https://doi.org/10.1109/jssc.2014.2312412
Publikováno v:
ISSCC
To obtain a 20cm-resolution image within a 15m distance using an X-band FMCW radar, an agile chirp frequency synthesizer phase-locked loop (FSPLL) with a wide chirp bandwidth (BW) greater than 750MHz and a short chirp period (Tm) less than 100µs is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2512f7cdba4d2454ecb1bcd05db3eb24
https://doi.org/10.1109/isscc.2016.7417995
https://doi.org/10.1109/isscc.2016.7417995
Publikováno v:
CICC
This paper describes a digital phase-locked loop (PLL) that realizes a peaking-free jitter transfer. That is the PLL's second-order transfer function does not have a closed-loop zero. Such a PLL does not exhibit overshoots in the phase step response
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::db2366ada9c94d732ecf8dc50e9522d1
https://doi.org/10.1109/cicc.2013.6658470
https://doi.org/10.1109/cicc.2013.6658470
Publikováno v:
CICC
An all-digital 90deg phase-shift DLL is proposed for 1.6 Gbps DDR interface by using a loop-embedded DCC and a binary phase detector with the lock range extended to 0~4pi radians. The DCC has a small delay and the fixed rising-edge property for loop-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e04457689b6e92b301bbaab7d55677d7
https://doi.org/10.1109/cicc.2007.4405755
https://doi.org/10.1109/cicc.2007.4405755