Zobrazeno 1 - 10
of 59
pro vyhledávání: '"Hun Hsien Chang"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1194-1199
An electrostatic discharge (ESD) protection design is proposed to solve the ESD protection challenge to the analog pins: for high-frequency or current-mode applications, By including an efficient power-rails clamp circuit in the analog input/output (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c3a699500ac784d97523cffa85f37112
https://doi.org/10.1109/4.859509
https://doi.org/10.1109/4.859509
Autor:
Ming-Dou Ker, Hun Hsien Chang
Publikováno v:
Solid-State Electronics. 44:425-445
The lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered by noise pulses when the ICs are operated in the application systems. A cascoded design is therefore propo
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5af334567f707ec087cb5245367c0186
https://doi.org/10.1016/s0038-1101(99)00247-6
https://doi.org/10.1016/s0038-1101(99)00247-6
Autor:
Hun Hsien Chang, Ming-Dou Ker
Publikováno v:
Journal of Electrostatics. 47:215-248
In this paper, the lateral SCR devices used in CMOS on-chip ESD protection circuits are reviewed. Such SCR devices had been found to be accidentally triggered on by noise pulses when the ICs are in the normal operating condition. A cascode design is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::ac6e81355e5fa76ab9591f1429dd7b54
https://doi.org/10.1016/s0304-3886(99)00037-6
https://doi.org/10.1016/s0304-3886(99)00037-6
Publikováno v:
Solid-State Electronics. 43:375-393
A novel dynamic-floating-gate technique is proposed to improve ESD robustness of the CMOS output buffers with small driving/sinking currents. This dynamic-floating-gate design can effectively solve the ESD protection issue which is due to the differe
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::42123b5442576070e6d54057f1be3823
https://doi.org/10.1016/s0038-1101(98)00262-7
https://doi.org/10.1016/s0038-1101(98)00262-7
Autor:
Hun-Hsien Chang, Jiin-Chuan Wu
Publikováno v:
IEEE Journal of Solid-State Circuits. 33:1572-1575
A high-speed complementary metal-oxide-semiconductor (CMOS) programmable divide-by-N frequency divider was proposed. Using a new end-of-count (EOC) detecting and reloading algorithm, the reloading delay is distributed over three clock cycles, which i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e363e7f6b7b68836f53c88fc40cdc3ad
https://doi.org/10.1109/4.720407
https://doi.org/10.1109/4.720407
Publikováno v:
IEEE Journal of Solid-State Circuits. 32:38-51
A novel electrostatic discharge (ESD) protection circuit, which combines complementary low-voltage-triggered lateral SCR (LVTSCR) devices and the gate-coupling technique, is proposed to effectively protect the thinner gate oxide of deep submicron CMO
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ca2dc709c3cb4d596c0ec2ccabeca2c
https://doi.org/10.1109/4.553176
https://doi.org/10.1109/4.553176
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 4:307-321
Capacitor-couple technique used to lower snapback-trigger voltage and to ensure uniform ESD current distribution in deep-submicron CMOS on-chip ESD protection circuit is proposed. The coupling capacitor is realized by a poly layer right under the wir
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::55f6e8201e3d57e161cb1f87211cc121
https://doi.org/10.1109/92.532032
https://doi.org/10.1109/92.532032
Publikováno v:
IEEE Transactions on Electron Devices. 43:588-598
There is one LVTSCR device merged with short-channel NMOS and another LVTSCR device merged with short-channel PMOS in a complementary style to offer effective and direct ESD discharging paths from the input or output pads to VSS and VDD power lines.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a433e2d211d9791aee76b92e8356d5f4
https://doi.org/10.1109/ted.1996.1210725
https://doi.org/10.1109/ted.1996.1210725
Autor:
Y.H. Huang, W. C. Chiou, Yi-Chun Shih, T. Y. Wang, W.J. Wu, Y.C. Lin, C.H. Chang, F.W. Tsai, C. H. Tung, S.P. Jeng, Kuo-Nan Yang, Doug C. H. Yu, M. F. Chen, Pang-Yen Tsai, Jing-Cheng Lin, E.B. Liao, Shang-Yun Hou, Hun-Hsien Chang, Y.L. Lin, T.J. Wu, Hung Jeng-Nan, C.L. Yu
Publikováno v:
2010 International Electron Devices Meeting.
Technology challenges and solutions in the development and fabrication of high-density three dimensional (3D) chip integration structures have been investigated. Critical 3D integrated circuit (IC) enabling technologies, such as through silicon via (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2ad4c97f122b261af4d84267041af778
https://doi.org/10.1109/iedm.2010.5703277
https://doi.org/10.1109/iedm.2010.5703277
Autor:
Winston Shue, Y.J. Lu, W.C. Chiou, C.H. Yu, Y.C. Lin, M. F. Chen, T.D. Wang, C.L. Yu, H.P. Hu, H.J. Tu, M.H. Tseng, K.M. Ching, Ding-Yuan Chen, Hun-Hsien Chang, C.S. Hsu, Ching-Wen Hsiao, W.J. Wu, Kuo-Nan Yang
Publikováno v:
2009 IEEE International Electron Devices Meeting (IEDM).
High density through-silicon-via (TSV) and cost-effective 3D die-to-wafer integration scheme are proposed as best-in-class foundry solutions for high-end CMOS chips at 28 nm node and beyond. Key processes include: TSV formation, extreme thinning of t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::362f97b7166362d453ce3ad4c60d7950
https://doi.org/10.1109/iedm.2009.5424350
https://doi.org/10.1109/iedm.2009.5424350