Výsledky vyhledávání - "Huiling Shang"

Outcome and Prognostic Factors of Laparoscopic Radical Hysterectomy and Pelvic Lymphadenectomy in 148 Patients With Stage IB1 Cervical Cancer

Autor: Guangyi Li, Feng Lin, Xiaojun Yang, Xiaojian Yan, Fei-Yun Zheng, Huiling Shang

Publikováno v: International Journal of Gynecological Cancer. 22:286-290

To evaluate the surgical, oncological outcome and prognostic factors of laparoscopic radical hysterectomy (LRH) and pelvic lymphadenectomy in patients with stage IB1 cervical cancer.Patients with IB1 cervical cancer undergoing LRH at the First People

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::16fb9cae813c62eb1c342278930d4f6d
https://doi.org/10.1097/igc.0b013e318233d549

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Investigation of Fixed Oxide Charge and Fin Profile Effects on Bulk FinFET Device Characteristics

Autor: Philip J. Oldiges, Dong-il Bae, Andreas Scholze, Huiling Shang, Peter Zeitzoff, Dechao Guo, Bomsoo Kim, Kang-ill Seo, Xin Sun, Theodorus E. Standaert, Neeraj Tripathi

Publikováno v: IEEE Electron Device Letters. 34:1485-1487

The effect of positive fixed oxide charge (Qf) on the electrical characteristics of bulk FinFET devices is investigated and newly addressed as a Fin scaling detractor. The aggressively scaled Fin width leads to abnormal subthreshold slope (SS) degrad

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6d09a2343da8ac251b3ceab52ac40fb4
https://doi.org/10.1109/led.2013.2285914

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Gate-Induced-Drain-Leakage Current in 45-nm CMOS Technology

Autor: David C. Ahlgren, Chu-Hsin Liang, Hyotae Choo, Victor Chan, Jun Yuan, Jae-Eun Park, Enhai Zhao, Xiaobin Yuan, R. Lindsay, Huiling Shang, Jing Wang, Terence B. Hook, Sung-Joon Park

Publikováno v: IEEE Transactions on Device and Materials Reliability. 8:501-508

Gate-induced-drain-leakage (GIDL) current in 45-nm state-of-the-art MOSFETs is characterized in detail. For the current technology node with a 1.2-V power-supply voltage, the GIDL current is found to increase in MOSFETs with higher channel-doping lev

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f341c6381cfab32417c8d74655f50c01
https://doi.org/10.1109/tdmr.2008.2002350

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High Mobility Strained Ge / SiGe PMOSFETs for High Performance CMOS

Autor: John A. Ott, Jack O. Chu, Huiling Shang, Stephen W. Bedell

Publikováno v: ECS Transactions. 3:679-686

Dramatic hole mobility enhancement of 4-25X has been demonstrated in compressively strained Ge p-channel MOSFETs - the highest mobility enhancement for hole carriers among all available options. This paper reviews the material properties of strained

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::24e37fbd319af5db5f28afe87ab8a105
https://doi.org/10.1149/1.2355863

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Germanium channel MOSFETs: Opportunities and challenges

Autor: Huiling Shang, Martin M. Frank, J. O. Chu, Evgeni Gusev, Kathryn W. Guarini, Meikei Ieong, Stephen W. Bedell

Publikováno v: IBM Journal of Research and Development. 50:377-386

This paper reviews progress and current critical issues with respect to the integration of germanium (Ge) surface-channel MOSFET devices as well as strained-Ge buried-channel MOSFET structures. The device design and scalability of strained-Ge buried-

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2dd3f1b47c81a60814b74606bc747443
https://doi.org/10.1147/rd.504.0377

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High performance 14nm SOI FinFET CMOS technology with 0.0174µm2 embedded DRAM and 15 levels of Cu metallization

Autor: E. Engbrecht, Edward P. Maciejewski, Christopher D. Sheraw, R. Divakaruni, Zhengwen Li, Allen H. Gabor, L. Economikos, Fernando Guarin, N. Zhan, H-K Lee, MaryJane Brodsky, Kenneth J. Stein, Siyuranga O. Koswatta, Y. Yang, Byeong Y. Kim, J. Hong, A. Bryant, Herbert L. Ho, Ruqiang Bao, Nicolas Breil, Babar A. Khan, E. Woodard, W-H. Lee, C-H. Lin, A. Levesque, Kevin McStay, V. Basker, Viraj Y. Sardesai, C. Tran, A. Ogino, Reinaldo A. Vega, C. DeWan, Shreesh Narasimha, J-J. An, Amit Kumar, A. Aiyar, Ravikumar Ramachandran, W. Wang, X. Wang, W. Nicoll, D. Hoyos, A. Friedman, Barry Linder, Yongan Xu, E. Alptekin, Cathryn Christiansen, S. Polvino, Han Wang, Scott R. Stiffler, G. Northrop, S. Saudari, J. Rice, Saraf Iqbal Rashid, Sunfei Fang, Michael V. Aquilino, Z. Ren, B. Kannan, Geng Wang, Noah Zamdmer, T. Kwon, Paul D. Agnello, Hasan M. Nayfeh, S. Jain, Robert R. Robison, M. Hasanuzzaman, J. Cai, L. Lanzerotti, D. Wehelle-Gamage, Basanth Jagannathan, J. Johnson, E. Kaste, Kai Zhao, Huiling Shang, Carl J. Radens, Shariq Siddiqui, Y. Ke, D. Ferrer, Ximeng Guan, D. Conklin, K. Boyd, K. Henson, Siddarth A. Krishnan, Bernard A. Engel, H. Dong, S. Mahajan, Unoh Kwon, Dominic J. Schepis, William Y. Chang, Liyang Song, Brian J. Greene, Chengwen Pei, S.-J. Jeng, Clevenger Leigh Anne H, Vijay Narayanan, C. Zhu, Wai-kin Li, Henry K. Utomo, Wei Liu, Dureseti Chidambarrao

Publikováno v: 2014 IEEE International Electron Devices Meeting.

We present a fully integrated 14nm CMOS technology featuring finFET architecture on an SOI substrate for a diverse set of SoC applications including HP server microprocessors and LP ASICs. This SOI finFET architecture is integrated with a 4th generat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::6233530b0b3fd6ddc14276a018716523
https://doi.org/10.1109/iedm.2014.7046977

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