Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Huan Yin Liu"'
Autor:
Huan Yin Liu, 劉桓吟
104
With the advances of the electronic packaging, 2.5D IC and 3D IC with Cu through silicon vias (copper TSVs) which can providing the improvement of circuit density and interconnect performance become a trend. In every 2.5D IC, there is a Cu T
With the advances of the electronic packaging, 2.5D IC and 3D IC with Cu through silicon vias (copper TSVs) which can providing the improvement of circuit density and interconnect performance become a trend. In every 2.5D IC, there is a Cu T
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/36dvh8
Autor:
Y. C. Chao, Meng-Kai Shih, Ming-Yi Tsai, J. H. Yeh, Dao-Long Chen, David Tarng, P. S. Huang, Huan-Yin Liu, Fila Tsai
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 19:615-621
With the trends of electronic packaging development toward small size, low-profile features, high-pin count, and high performance, the 3D IC (Three-dimensional Integrated Circuits) or stacked-die packages have been gaining popularity. For such packag
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f9a8622c7c1e3f3e26fda353a23fbf12
https://doi.org/10.1109/tdmr.2019.2937988
https://doi.org/10.1109/tdmr.2019.2937988
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 18:450-455
This paper aims to investigate the thermally induced warpage and stress of 2.5D packages with and without a reinforced metal frame experimentally and numerically. The consistent results between shadow moire experiment and the finite element method (F
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::471b840241613a2321ec977cba3ab5ed
https://doi.org/10.1109/tdmr.2018.2865013
https://doi.org/10.1109/tdmr.2018.2865013
Publikováno v:
IEEE Transactions on Device and Materials Reliability. 17:364-370
The 2.5-D IC packaging technology is to apply a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform to interconnect and integrate heterogeneous and homogeneous chips horizontally and vertically. The existing Cu TSVs might make the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2a5e8f1fdd49505b2af6e7b44a5a942
https://doi.org/10.1109/tdmr.2017.2683505
https://doi.org/10.1109/tdmr.2017.2683505
Determination of strength of Si interposers using PoEF test associated with acoustic emission method
Publikováno v:
2016 11th International Microsystems, Packaging, Assembly and Circuits Technology Conference (IMPACT).
Semiconductor companies have developed 2.5D IC integration technology, which applies a silicon interposer with Cu through silicon vias (Cu TSVs) as a platform for interconnecting and integrating heterogeneous chips horizontally and vertically as a tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::865f136a0f21e3d3798c99fd4b53dcd2
https://doi.org/10.1109/impact.2016.7800067
https://doi.org/10.1109/impact.2016.7800067