Výsledky vyhledávání - "Huan Shun Huang"

A 0.5-V 28-nm 256-kb Mini-Array Based 6T SRAM With Vtrip-Tracking Write-Assist

Autor: Wei-Sheng Peng, Kuen-Di Lee, Po-Tsang Huang, Shang-Lin Wu, Sheng-Chi Lung, Ming-Hsien Tu, Ching-Te Chuang, Huan-Shun Huang, Kuang-Yu Li, Yung-Shin Kao, Wei Hwang

Publikováno v: IEEE Transactions on Circuits and Systems I: Regular Papers. 64:1791-1802

This paper presents a 28-nm 256-kb 6T static random access memory operating down to near-threshold regime. The cell array is built on foundry 4-by-2 mini-array with split single-ended large signal sensing to enable an ultra-short local bit-line of 4-

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::860ca831f5c59066616d86125b97cbea
https://doi.org/10.1109/tcsi.2017.2681738

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A 0.35 V, 375 kHz, 5.43 µW, 40 nm, 128 kb, symmetrical 10T subthreshold SRAM with tri-state bit-line

Autor: Ming Hsien Tu, Shang-Lin Wu, Yung Shin Kao, Ching-Te Chuang, Huan Shun Huang, Kuen Di Lee, Chien-Yu Lu

Publikováno v: Microelectronics Journal. 51:89-98

This paper presents a disturb-free 10T subthreshold SRAM cell with fully-symmetrical structure and tri-state pre-charge free bit-line (BL). The disturb-free feature facilitates bit-interleaving architecture that can reduce multiple-bit errors in a si

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7fac3f497ce2ad9b66f910ad82667d7e
https://doi.org/10.1016/j.mejo.2016.02.011

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A 0.325 V, 600-kHz, 40-nm 72-kb 9T Subthreshold SRAM with Aligned Boosted Write Wordline and Negative Write Bitline Write-Assist

Autor: Shyh-Jye Jou, Chung-Ping Huang, Yung-Shin Kao, Ya-Ping Wu, Chien-Yu Lu, Paul-Sen Kan, Huan-Shun Huang, Kuen-Di Lee, Ming-Hsien Tu, Ching-Te Chuang

Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 23:958-962

This brief presents a two-port disturb-free 9T subthreshold static random access memory (SRAM) cell with independent single-ended read bitline and write bitline (WBL) and cross-point data-aware write structure to facilitate robust subthreshold operat

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7934e8842a2b550eaf80744da22553e4
https://doi.org/10.1109/tvlsi.2014.2318518

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Perceptual Zero-Tree Coding with Efficient Optimization for Embedded Platforms

Autor: Yen-Lin Chen, C.J. Chen, Bing-Fei Wu, Jenq-Haur Wang, Huan-Shun Huang

Publikováno v: Journal of Applied Research and Technology. 11:487-495

This study proposes a block-edge-based perceptual zero-tree coding (PZTC) method, which is implemented with efficient optimization on the embedded platform. PZTC combines two novel compression concepts for coding efficiency and quality: block-edge de

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::5ecf8115db5701cf24038d3a66958ee9
https://doi.org/10.1016/s1665-6423(13)71556-6

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A 0.33-V, 500-kHz, 3.94-$\mu\hbox{W}$ 40-nm 72-Kb 9T Subthreshold SRAM With Ripple Bit-Line Structure and Negative Bit-Line Write-Assist

Autor: Ching-Te Chuang, Yung-Shin Kao, Ya-Ping Wu, Huan-Shun Huang, Shyh-Jye Jou, Wei Hwang, Chien-Yu Lu, Ming-Hsien Tu, Yuh-Jiun Lin, Hao-I Yang, Kuen-Di Lee

Publikováno v: IEEE Transactions on Circuits and Systems II: Express Briefs. 59:863-867

This paper presents an ultra-low-power 72-Kb 9T static random-access memory (SRAM) with a ripple bit-line (RPBL) structure and negative bit-line (NBL) write-assist. The RPBL scheme provides over 40% read access performance improvement for VDD below 0

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::59c2a971d2c5d63e493c84ad8901fcee
https://doi.org/10.1109/tcsii.2012.2231017

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A Single-Ended Disturb-Free 9T Subthreshold SRAM With Cross-Point Data-Aware Write Word-Line Structure, Negative Bit-Line, and Adaptive Read Operation Timing Tracing

Autor: Jihi-Yu Lin, Wei-Chiang Shih, Ming-Chien Tsai, Ching-Te Chuang, Shyh-Jye Jou, Ming-Hsien Tu, Huan-Shun Huang, Chien-Yu Lu, Meng-Hsueh Wang, Yuh-Jiun Lin, Kuen-Di Lee

Publikováno v: IEEE Journal of Solid-State Circuits. 47:1469-1482

This paper presents a novel single-ended disturb-free 9T subthreshold SRAM cell with cross-point data-aware Write word-line structure. The disturb-free feature facilitates bit-interleaving architecture, which can reduce multiple-bit upsets in a singl

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::bd783eb5c6527b83a5514c06b956efde
https://doi.org/10.1109/jssc.2012.2187474

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Dissertation/ Thesis

An Exploratory Study on Forward Integration Strategy of Electronic Component Industry

Autor: Huan-Shun Huang, 黃煥順

103
Under the background of gross profit reducing and product life cycle become shorter and shorter, lots of manufacturers of electronic component industry in Taiwan conceived a strategy of forward integration in order to increase the profit of

Externí odkaz: http://ndltd.ncl.edu.tw/handle/63684761283746873724

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A 40nm 1.0Mb pipeline 6T SRAM with variation-tolerant Step-Up Word-Line and Adaptive Data-Aware Write-Assist

Autor: Chi-Shin Chang, Shyh-Jye Jou, Cheng-Yo Cheng, Nan-Chun Lien, Hao-I Yang, Wei-Chiang Shih, Paul-Sen Kan, Chien-Hen Chen, Wei-Nan Liao, Yi-Wei Lin, Jian-Hao Wang, Ming-Hsien Tu, Ching-Te Chuang, Kuen-Di Lee, Yong-Jyun Hu, Wei Hwang, Wei-Chang Wang, Chia-Cheng Chen, Huan-Shun Huang

Publikováno v: ISCAS

We present a 1.0Mb pipeline 6T SRAM in 40nm Low-Power CMOS technology. The design employs a variation-tolerant Step-Up Word-Line (SUWL) to improve the Read Static Noise Margin (RSNM) without compromising the Read performance and Write-ability. The Wr

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::cd08d04ceaf2c5ba11e243a1a6b088e9
https://doi.org/10.1109/iscas.2013.6572134

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A 55nm 0.55v 6T SRAM with variation-tolerant dual-tracking word-line under-drive and data-aware write-assist

Autor: Hao-I Yang, Huan-Shun Huang, Chia-Cheng Chen, Chi-Shin Chang, Willis Shih, Yi-Wei Lin, Wei Hwang, Geng-Cing Lin, Ching-Te Chuang

Publikováno v: ISLPED

We present a 55nm 128Kb 6T SRAM with a variation-tolerant dual-tracking Word-Line Under-Drive (WLUD) to improve the RSNM and a Data-Aware Write-Assist (DAWA) scheme. Error free full functionality without redundancy is achieved from 1.5V down to 0.55V

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::071bf35d39ca5f49df1d016aba3cf701
https://doi.org/10.1145/2333660.2333682

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