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pro vyhledávání: '"Hsu-Chieh Lee"'
Autor:
Hsu-Chieh Lee, 李緒頡
99
In today''s IC production, the design processes of chip, package, and board are separate from each other. However, the lack of information from other domains dramatically increases the design difficulty and reduces the quality of the product.
In today''s IC production, the design processes of chip, package, and board are separate from each other. However, the lack of information from other domains dramatically increases the design difficulty and reduces the quality of the product.
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/48940177718280905195
Autor:
Wen-Chi Tseng, Ming-Jun Wang, Yi-Hung Wu, Hsu-Chieh Lee, Hong-Yi Fang, Chung-Ting Hsu, Chao-Nan Chen, Tsuei-Yun Fang
Publikováno v:
International journal of biological macromolecules. 112
d -Allulose 3-epimerase (DAEase) catalyzes the epimerization between d -fructose and d -allulose. We had PCR-cloned and overexpressed the gene encoding Agrobacterium sp. ATCC 31749 DAEase (AsDAEase) in Escherichia coli. A high yield of active AsDAEas
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 32:1347-1356
To accommodate the ever-growing pin number of complex printed circuit board (PCB) designs, the staggered pin array is introduced for modern designs with higher pin density. However, the escape routing for staggered pin arrays, which is a key componen
Publikováno v:
ASP-DAC
For high-performance synchronous systems, non-uniform/non-ideal supply voltages of buffers (e.g., due to IRdrop) may incur a large clock skew and thus serious performance degradation. This paper addresses this problem and presents the first symmetric
Autor:
Yao-Wen Chang, Chin-Fang Shen, Chen-Feng Chang, Hsu-Chieh Lee, Webber Lee, Yuan-Kai Ho, I-Jye Lin
Publikováno v:
DAC
The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal int
Autor:
Hsu-Chieh Lee, Yao-Wen Chang
Publikováno v:
DAC
In today's IC production, the design processes of chips, packages, and boards are typically separate from each other. The lack of information from other domains causes significant design convergence problems and greatly reduces design quality. In thi
Publikováno v:
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Publikováno v:
2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
Autor:
Po-Wei Lee, Hsu-Chieh Lee, Yuan-Kai Ho, Yao-Wen Chang, Chen-Feng Chang, I-Jye Lin, Chin-Fang Shen
Publikováno v:
DAC: Annual ACM/IEEE Design Automation Conference; Jun2012, p1088-1093, 6p
Publikováno v:
2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD); 2011, p306-309, 4p