Zobrazeno 1 - 10
of 18
pro vyhledávání: '"Hsing-jen Wann"'
Autor:
George Anthony Sai-Halasz, Douglas A. Buchanan, Shih-Hsien Lo, Yuan Taur, Shalom J. Wind, Wei Chen, Hsing-Jen Wann, Hon-Sum Philip Wong, Khalid EzzEldin Ismail, R. Viswanathan, David J. Frank
Publikováno v:
Proceedings of the IEEE. 85:486-504
Starting with a brief review on 0.1-/spl mu/m (100 nm) CMOS status, this paper addresses the key challenges in further scaling of CMOS technology into the nanometer (sub-100 nm) regime in light of fundamental physical effects and practical considerat
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6bb9bd14151f642e0adfab427e447bec
https://doi.org/10.1109/5.573737
https://doi.org/10.1109/5.573737
Publikováno v:
IEEE Electron Device Letters. 17:202-204
Based a new empirical mobility model that is solely dependent on V/sub gs/, V/sub t/, and T/sub ox/ and a corresponding saturation drain current (I/sub dsat/) model, the impact of device scaling and power supply voltage change on CMOS inverter's perf
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fc53ecf45c9f4ef4e61af6609088af97
https://doi.org/10.1109/55.491829
https://doi.org/10.1109/55.491829
Publikováno v:
IEEE Electron Device Letters. 17:145-147
Based on a new empirical mobility model which is solely dependent on V/sub gs/, V/sub t/ and T/sub ox/, a corresponding semiempirical I/sub dsat/ model for n-MOSFET including velocity saturation, mobility degradation due to increased vertical effecti
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e22771eede21d7626d3267443731b7a9
https://doi.org/10.1109/55.485195
https://doi.org/10.1109/55.485195
Autor:
Chenming Hu, Hsing-Jen Wann
Publikováno v:
IEEE Electron Device Letters. 16:491-493
Ultra-thin tunnel oxide can conduct very high current through oxide via direct tunneling, and charge-to-breakdown increases dramatically due to less oxide damage. These facts point to a possibility of using thin tunnel oxide in the floating-gate devi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9d58df207d2032510437bed488dbfa25
https://doi.org/10.1109/55.468277
https://doi.org/10.1109/55.468277
Publikováno v:
1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers.
The peak channel electric field E/sub m/ of MOSFET is a monitor of the hot-carrier-induced device degradation. The quasi-two-dimensional model for bulk MOSFET predicts E/sub m/ to be a function of device parameters including the drain junction depth
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5191c88b66eb6b947ca586e21a630dc1
https://doi.org/10.1109/vtsa.1993.263644
https://doi.org/10.1109/vtsa.1993.263644
Autor:
Chenming Hu, Hsing-Jen Wann
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
We propose a capacitorless DRAM (CDRAM) cell on SOI substrate with large READ current (>100 /spl mu/Aspl mu/m), small cell size, and simple fabrication process. PISCES simulations are used to analyze the memory cell operations. The CDRAM cell size is
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b7a50800819aea01aaf3e8f3c528d60
https://doi.org/10.1109/iedm.1993.347280
https://doi.org/10.1109/iedm.1993.347280
Publikováno v:
Proceedings of 1993 IEEE International SOI Conference.
MOSFETs built on the SOI structure exhibit superior short channel behaviors over the bulk MOSFETs. They also have other advantages such as reduction of the junction capacitance, radiation hardness and ease for device isolation. The SOI MOSFET is a pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8a9cafa2bf453632b4306d7197d56560
https://doi.org/10.1109/soi.1993.344568
https://doi.org/10.1109/soi.1993.344568
Publikováno v:
1995 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers.
With the scaling of the power supply voltage V/sub DD/ in low voltage and low power VLSI, the threshold voltage of the MOSFET device needs to be reduced to retain the device performance in terms of current driving capability and switching speed. Rece
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7638a09cbb88b6e9c61364e49d38d329
https://doi.org/10.1109/vtsa.1995.524654
https://doi.org/10.1109/vtsa.1995.524654
Publikováno v:
Symposium 1993 on VLSI Technology.
With increasing memory density of Flash EEPROM, the gate-induced drain leakage (GIDL) due to band-to-band tunneling during erase can become an important concern since millions of transistors are erased at the same time. In the common scheme of the do
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6d7ba731f30ca1d7fc4cf231a0a6c3e7
https://doi.org/10.1109/vlsit.1993.760255
https://doi.org/10.1109/vlsit.1993.760255
Publikováno v:
1992 International Technical Digest on Electron Devices Meeting; 1992, p147-150, 4p