Zobrazeno 1 - 10
of 34
pro vyhledávání: '"Hsing-Chung Liang"'
Autor:
Katherine Shu-Min Li, Xu-Hao Jiang, Leon Li-Yang Chen, Sying-Jyan Wang, Andrew Yi-Ann Huang, Jwu E. Chen, Hsing-Chung Liang, Chun-Lung Hsu
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 35:291-299
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0539e6330261f546bc3b47802a367540
https://doi.org/10.1109/tsm.2022.3159246
https://doi.org/10.1109/tsm.2022.3159246
Autor:
Katherine Shu-Min Li, Leon Li-Yang Chen, Peter Yi-Yu Liao, Sying-Jyan Wang, Andrew Yi-Ann Huang, Leon Chou, Nova Cheng-Yeh Tsai, Ken Chau-Cheung Cheng, Gus Chang-Hung Han, Chen-Shiun Lee, Jwu E. Chen, Hsing-Chung Liang, Chung-Lung Hsu
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 35:272-281
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e63787231752b535207658a9b31591e0
https://doi.org/10.1109/tsm.2022.3146857
https://doi.org/10.1109/tsm.2022.3146857
Autor:
Nova Cheng-Yen Tsai, Katherine Shu-Min Li, Leon Chou, Ji-Wei Li, Leon Li-Yang Chen, Andrew Yi-Ann Huang, Hsing-Chung Liang, Jwu E. Chen, Chen-Shiun Lee, Chun-Lung Hsu, Sying-Jyan Wang, Ken Chau-Cheung Cheng
Publikováno v:
IEEE Transactions on Semiconductor Manufacturing. 34:161-167
Wafer test is carried out after integrated circuits (IC) fabrication to screen out bad dies. In addition, the results can be used to identify problems in the fabrication process and improve manufacturing yield. However, the wafer test itself may indu
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cdb6a20e453a616bf09e0e03effcfdf9
https://doi.org/10.1109/tsm.2021.3065405
https://doi.org/10.1109/tsm.2021.3065405
Autor:
Leon Li-Yang Chen, Katherine Shu-Min Li, Jwu E. Chen, Xu-Hao Jiang, Andrew Yi-Ann Huang, Chun-Lung Hsu, Hsing-Chung Liang, Sying-Jyan Wang
Publikováno v:
ITC
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::85b7938ac535c59f8a40865c26b64e06
https://doi.org/10.1109/itc50571.2021.00029
https://doi.org/10.1109/itc50571.2021.00029
Autor:
Peter Yi-Yu Liao, Gus Chang-Hung Han, Sying-Jyan Wang, Andrew Yi-An Huang, Katherine Shu-Min Li, Nova Cheng-Yen Tsai, Leon Chou, Jwu E. Chen, Chun-Lung Hsu, Ken Chau-Cheung Cheng, Hsing-Chung Liang, Leon Li-Yang Chen
Publikováno v:
ETS
we propose an automatic wafer defect maps detection method based on unsupervised learning. There is no need for human labeling, and similar defect clusters are identified automatically without human intervention. As a result, the process is less erro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0bfc17b151d323e607cae974278ca6d5
https://doi.org/10.1109/ets50041.2021.9465457
https://doi.org/10.1109/ets50041.2021.9465457
Autor:
Hsing-Chung Liang, Hua-Ren Li
Publikováno v:
ETS
Test generation and fault simulation are essential in VLSI automatic test pattern generation (ATPG). Parallel computing on GPU gives another way to improve work performance. Thousands of concurrent threads can be launched simultaneously within GPU. D
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::59ffed0386c12ce935c0ae97868bd8b7
https://doi.org/10.1109/ets50041.2021.9465466
https://doi.org/10.1109/ets50041.2021.9465466
Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis
Autor:
Ken Chau-Cheung Cheng, Nova Cheng-Yen Tsai, Peter Yi-Yu Liao, Leon Chou, Ji-Wei Li, Andrew Yi-Ann Huang, Hsing-Chung Liang, Jwu E. Chen, Katherine Shu-Min Li, Leon Li-Yang Chen, Sying-Jyan Wang, Chen-Shiun Lee
Publikováno v:
DATE
Wafer defect maps provide precious information of fabrication and test process defects, so they can be used as valuable sources to improve fabrication and test yield. This paper applies artificial intelligence based pattern recognition techniques to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::388720e0b20bd7e63d28f4b6b35350e2
https://doi.org/10.23919/date48585.2020.9116546
https://doi.org/10.23919/date48585.2020.9116546
Autor:
Hsing-Chung Liang
Publikováno v:
Journal of Circuits, Systems and Computers. 18:81-95
This paper introduces a novel method of identifying better representatives of faulty cells in a memory map to help judge unrepairability and provide economical repair solutions. These representatives, called leading elements (LE), are classified into
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3b53691caf50975e934549793276bdd6
https://doi.org/10.1142/s0218126609004946
https://doi.org/10.1142/s0218126609004946
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 27:1693-1697
This paper proposes a novel type of modified Booth multiplier and generates constant test pairs for single transition delay faults (TDFs) in multipliers of various sizes. All TDFs of the multipliers at cell and gate levels are C-testable with 10 and
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0a5b33d823a9124f78cbe178328c828
https://doi.org/10.1109/tcad.2008.927761
https://doi.org/10.1109/tcad.2008.927761
Publikováno v:
IEEE Transactions on Reliability. 54:358-365
In this paper, we discuss some strategies for identifying unrepairable memories, and from that to introduce a novel theorem that can make more precise identification. A new algorithm for searching repair solutions is also proposed, which characterize
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3a52dc4ea1347dc34ff506605fb47843
https://doi.org/10.1109/tr.2005.847248
https://doi.org/10.1109/tr.2005.847248