Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Hsing Ning Liu"'
Autor:
Channing Cheng-Lin Yang, John H Lau, Gary Chang-Fu Chen, Jones Yu-Cheng Huang, Andy Peng, Hsing-Ning Liu, YH Chen, Tzyy-Jang Tseng
Publikováno v:
IMAPSource Proceedings. 2022
The design, materials, process, and fabrication of a hybrid substrate for the heterogeneous integration of chips with 50μm-pitch (minimum) by fan-out chip-last panel-level packaging are presented. The hybrid substrate consists of a fine metal linewi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e61cf6b1ecb5c3a8f8a3124d37cfe2f0
https://doi.org/10.4071/001c.74589
https://doi.org/10.4071/001c.74589
Autor:
Tony Chia-Yu Peng, John H. Lau, Cheng-Ta Ko, Paul Lee, Eagle Lin, Kai-Ming Yang, Bruce Puru Lin, Tim Xia, Leo Chang, Hsing-Ning Liu, Curry Lin, Tzu Nien Lee, Jason Wong, Mike Ma, Tzyy-Jang Tseng
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 12:469-478
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ef1462fe60f93e69f4abb75639bcedb3
https://doi.org/10.1109/tcpmt.2022.3151848
https://doi.org/10.1109/tcpmt.2022.3151848
Autor:
Ricky Tsun-Sheng Chou, John H Lau, Gary Chang-Fu Chen, Jones Yu-Cheng Huang, Channing Cheng-Lin Yang, Hsing-Ning Liu, Tzyy-Jang Tseng
Publikováno v:
International Symposium on Microelectronics. 2021:000124-000129
In this study, the reliability of chiplets heterogeneous integration on a 2.3D hybrid substrate using solder joint and underfill is investigated. Emphasis is placed on the thermal cycling test and drop test of the structure. The test results are plot
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5f0d9fcd7a8a0145dbc56690c8d8b544
https://doi.org/10.4071/1085-8024-2021.1.000124
https://doi.org/10.4071/1085-8024-2021.1.000124
Autor:
Hsing-Ning Liu, Channing Cheng-Lin Yang, John H. Lau, Gary Chang-Fu Chen, Ricky Tsun-Sheng Chou, Jones Yu-Cheng Huang, Tzyy-Jang Tseng
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:1301-1309
The panel-level redistribution-layer (RDL)-first fan-out packaging for hybrid substrate is studied. Emphasis is placed on the process, materials, design, and fabrication of: 1) heterogeneous integration of one large chip and one small chip with 50- $
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ae92d8a335940a965edc0e3f4947dba6
https://doi.org/10.1109/tcpmt.2021.3096786
https://doi.org/10.1109/tcpmt.2021.3096786
Autor:
Yan-Jun Fan, John H. Lau, Kai-Ming Yang, Hsing-Ning Liu, Tzvy-Jang Tseng, Eagle Lin, Puru Bruce Lin, Curry Lin, Leo Chang, Jean-Jou Chen, Po-Chun Huang, Cheng-Ta Ko, Tim Xia, Winnie Lu, Chia-Yu Peng
Publikováno v:
Journal of Microelectronics and Electronic Packaging. 18:29-39
In this study, the reliability of the solder joints of a heterogeneous integration of one large chip (10 × 10 mm) and two smaller chips (7 × 5 mm) by a fan-out method with a redistribution layer-first substrate fabricated on a 515 × 510-mm panel i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9b8a304f5b03066bbe5ed60b583c39ef
https://doi.org/10.4071/imaps.1419800
https://doi.org/10.4071/imaps.1419800
Autor:
Tim Xia, David Cheng, Kai-Ming Yang, Yan-Jun Fan, Puru Bruce Lin, Tzvy-Jang Tseng, John H. Lau, Winnie Lu, Cheng-Ta Ko, Chia-Yu Peng, Curry Lin, Leo Chang, Hsing Ning Liu, Eagle Lin
Publikováno v:
Journal of Microelectronics and Electronic Packaging. 18:67-80
In this study, the reliability of the solder joints of a six-side molded panel-level chip-scale package (PLCSP) is investigated. Emphasis is placed on the thermal cycling test (−55°C Δ 125°C, 50-min cycle) of the six-side molded PLCSP on a print
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::462aa0ceca7feed717806ec4f7862fcc
https://doi.org/10.4071/imaps.1421341
https://doi.org/10.4071/imaps.1421341
Autor:
Gary Chang-Fu Chen, John H Lau, Channing Cheng-Lin Yang, Jones Yu-Cheng Huang, Andy Yan-Jia Peng, Hsing-Ning Liu, Tzyy-Jang Tseng, Ming Li
Publikováno v:
2022 IEEE 72nd Electronic Components and Technology Conference (ECTC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b08ecc031bef1bf9b7474aa04c416a8e
https://doi.org/10.1109/ectc51906.2022.00013
https://doi.org/10.1109/ectc51906.2022.00013
Autor:
John H. Lau, Cheng-Ta Ko, Tzvy-Jang Tseng, Chia-Yu Peng, Kai-Ming Yang, Tim Xia, Puru Bruce Lin, Eagle Lin, Leo Chang, Hsing Ning Liu, Curry Lin, David Cheng, Winnie Lu
Publikováno v:
Journal of Microelectronics and Electronic Packaging. 17:111-120
In this study, the design, materials, process, assembly, and reliability of a six-side molded panel-level chip-scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the redistribution layers (RDLs) of the PLCSP on a large temp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2f97c82b7c0e476e82cade1f0484b4ac
https://doi.org/10.4071/imaps.1226533
https://doi.org/10.4071/imaps.1226533
Autor:
Eagle Lin, Kai-Ming Yang, John H. Lau, Curry Lin, Leo Chang, Puru Bruce Lin, David Cheng, Tim Xia, Winnie Lu, Hsing Ning Liu, Chia-Yu Peng, Tzvy-Jang Tseng, Cheng-Ta Ko
Publikováno v:
International Symposium on Microelectronics. 2020:000057-000066
In this study, the design, materials, process, assembly, and reliability of a 6-side molded panel-level chip scale package (PLCSP) are presented. Emphasis is placed on the fabrication of the RDLs (redistribution layers) of the PLCSP on a large tempor
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d2e5d95c197a5b5390a5385f12cd8f43
https://doi.org/10.4071/2380-4505-2020.1.000057
https://doi.org/10.4071/2380-4505-2020.1.000057
Autor:
Tim Xia, Cheng-Ta Ko, David Cheng, Kai-Ming Yang, John H. Lau, Leo Chang, Tzyy-Jang Tseng, Eagle Lin, Tony Chia-Yu Peng, Hsing Ning Liu, Puru Bruce Lin
Publikováno v:
IEEE Transactions on Components, Packaging and Manufacturing Technology. 10:1110-1124
In this study, a very high-throughput and low-cost packaging method for fabricating the fan-in chip-scale package is presented. Emphasis is placed on the utilization of the existing printed circuit board (PCB) panel carriers and the corresponding PCB
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7c47a77cd9f2b8e31723a1552085a3f4
https://doi.org/10.1109/tcpmt.2020.2996255
https://doi.org/10.1109/tcpmt.2020.2996255