Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Hsiang-Yu Shih"'
Autor:
Hsiang-Yu Shih, 施翔于
106
This thesis demonstrates two research topics for ROM-less DDFS (direct digital frequency synthesizer), including a 4-stage pipeline ROM-less DDFS design using equal division parabolic polynomial interpolation method, which is carried out by
This thesis demonstrates two research topics for ROM-less DDFS (direct digital frequency synthesizer), including a 4-stage pipeline ROM-less DDFS design using equal division parabolic polynomial interpolation method, which is carried out by
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/a65xpn
Autor:
Hsiang-Yu Shih, 施翔宇
94
The study attempts to explain the spreads over three-month LIBOR rates on catastrophe bonds using regression models. Transactions from 1997 to 2005 are all analyzed by two empirical pricing models, namely the log LFC Model and Aggregate Model
The study attempts to explain the spreads over three-month LIBOR rates on catastrophe bonds using regression models. Transactions from 1997 to 2005 are all analyzed by two empirical pricing models, namely the log LFC Model and Aggregate Model
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/21142204027652608454
Publikováno v:
Journal of Nanoscience and Nanotechnology. 21:6082-6087
The increase of harmful carbon monoxide (CO) caused by incomplete combustion can affect human health even lead to suffocation. Therefore reducing the CO discharged by vehicles or factories is urgent to improve the air quality. The spinel cobalt (II,
Publikováno v:
Journal of nanoscience and nanotechnology. 21(12)
The increase of harmful carbon monoxide (CO) caused by incomplete combustion can affect human health even lead to suffocation. Therefore reducing the CO discharged by vehicles or factories is urgent to improve the air quality. The spinel cobalt (II,
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 27:2464-2468
In this brief, a four-stage pipeline read only memory (ROM)-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed. To attain higher spurious-free dynamic range (SFDR) and faster clock rate, the hardware cost a
Autor:
Chua-Chin Wang, Hsiang-Yu Shih
Publikováno v:
2018 Electrical Power, Electronics, Communications, Controls and Informatics Seminar (EECCIS).
A dynamic power estimation method for critical logic cirucits used in ROM-less direct digital frequency synthesizer (DDFS) designs is proposed, including the analysis of switching activity of adders, shifters, and multipliers. Most important of all,
Publikováno v:
2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).
A 4-stage pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this work. To attain higher SFDR (spurious free dynamic range) and faster clock rate, the hardware cost and delay using different
Publikováno v:
ISOCC
A pipeline ROM-less direct digital frequency synthesizer (DDFS) with equal division interpolation is proposed in this investigation. In order to get higher SFDR and faster clock rate, different segments with various interpolation equations are analyz
Autor:
Hsiang-Yu, Shih
Thesis (M.A.)--National Taiwan University Graduate Institute of Finance
Includes bibliographical references
Includes bibliographical references