Zobrazeno 1 - 3
of 3
pro vyhledávání: '"Howard S. Landis"'
Autor:
Anda Mocuta, Anthony I. Chou, Frank D. Tamweber, D. Lea, Jie Deng, J. A. Culp, Nivo Rovedo, H. Trombley, E. J. Nowak, Yue Liang, Woo-Hyeong Lee, K. Rim, B. A. Goplen, Sadanand V. Deshpande, William K. Henson, Brian J. Greene, Xiaojun Yu, Howard S. Landis, Dustin K. Slisher, L. R. Logan, Ming Cai, Oleg Gluschenkov, J. Sim, Paul Chang, Noah Zamdmer
Publikováno v:
2011 International Electron Devices Meeting.
We report a detailed study of the impact of systematic across-chip variation (ACV) on chip level power-performance. We propose a metric to capture impact of ACV on chip-level leakage quantitatively. Product power-performance can be optimized by minim
Autor:
Micheal Leach, William J. Cote, Stephen E. Luce, Carter Welling Kaanta, William R. Hill, Howard S. Landis, Charles W. Koburger, Cheryl A. Hoffman, Walter Frederick Lange, Peter J Burke
Publikováno v:
Thin Solid Films. 220:1-7
Planarization by chemical-mechanical polishing (CMP) has been exploited by IBM in the development and manufacture of CMOS products since 1985. Among the products that use this technology are the 4-Mbit DRAM (which uses polysilicon, oxide, tungsten-li
Autor:
S. Wolff, D.J. Poindexter, C.W. Kaanta, J.G. Ryan, John Edward Cronin, Howard S. Landis, C.W. Pollard, William R. Hill, S.G. Bombardier, William J. Cote, G.H. Ross, G. Kerszykowski
Publikováno v:
1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference.
Escalating density, performance, and (perhaps most importantly) manufacturing requirements associated with ULSI semiconducting wiring, necessitate a metamorphosis in interconnection technology. To meet these needs, an inlaid fully integrated wiring t