Zobrazeno 1 - 10
of 11
pro vyhledávání: '"Hossein Sabaghian-Bidgoli"'
A Petri-net-based communication-aware modeling for performance evaluation of NOC application mapping
Publikováno v:
The Journal of Supercomputing. 76:9246-9269
Advances in digital system manufacturing and increasing demand for high-speed applications have urged designers on using multiprocessor systems. Network on chip (NOC) is an important architecture used for implementing multiprocessor systems. The main
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a5dbd843b87e9ce9ac63896c749ebba6
https://doi.org/10.1007/s11227-020-03207-z
https://doi.org/10.1007/s11227-020-03207-z
Publikováno v:
Canadian Journal of Electrical and Computer Engineering. 43:100-110
Due to the growing complexity of today’s digital circuits, the speed of fault simulation has become increasingly important. Although critical path tracing (CPT) is faster than conventional methods, it is not fast enough for fault simulation of comp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e71a4bd2000bcc205935194b458282bc
https://doi.org/10.1109/cjece.2019.2950280
https://doi.org/10.1109/cjece.2019.2950280
Autor:
Farzaneh Zokaee, Hossein Sabaghian-Bidgoli, Zainalabedin Navabi, Vahid Janfaza, Payman Behnam
Publikováno v:
HLDVT
Along with advances in modern VLSI technology, delay faults are becoming ever more important. On the other hand, the strength of SAT-solver engines has made them an attractive means for solving many Computer Aided Design (CAD) problems. This paper pr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c830a1b68bb2885cce858e33902b40cb
https://doi.org/10.1109/hldvt.2017.8167458
https://doi.org/10.1109/hldvt.2017.8167458
Publikováno v:
EWDTS
This paper presents a hybrid history-based test generation mechanism that intermittently applies partial-test vectors to reduce test application time. Test generation is done by looking into the results of the circuit under test that are used later a
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f5848d9693c988e961a83b9031e9b998
https://doi.org/10.1109/ewdts.2017.8110140
https://doi.org/10.1109/ewdts.2017.8110140
Publikováno v:
ISVLSI
Fault diagnosis is one of the most important phases in the VLSI design cycle. This paper proposes a probabilistic solution for the fault diagnosis in the sequential scan-based circuits. Our approach uses a signal probability analysis to score and ran
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::cbe3c903bd469cbabc713700fe3e8ef9
https://doi.org/10.1109/isvlsi.2017.101
https://doi.org/10.1109/isvlsi.2017.101
Publikováno v:
Canadian Journal of Electrical and Computer Engineering. 37:192-202
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fe2f5510e54ee5a18be65b97d7063179
https://doi.org/10.1109/cjece.2014.2326054
https://doi.org/10.1109/cjece.2014.2326054
Publikováno v:
Journal of Computational and Theoretical Nanoscience. 8:1259-1263
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e0c737c3b7bb40eefca11b1f003cdc99
https://doi.org/10.1166/jctn.2011.1807
https://doi.org/10.1166/jctn.2011.1807
Publikováno v:
Journal of Computational and Theoretical Nanoscience. 6:1706-1708
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::68fb220484285794f97356f0a16299e6
https://doi.org/10.1166/jctn.2009.1235
https://doi.org/10.1166/jctn.2009.1235
Autor:
Payman Behnam, Hossein Sabaghian-Bidgoli, Kamyar Mohajerani, Bijan Alizadeh, Zainalabedin Navabi
Publikováno v:
EWDTS
In today's technology, verification and debugging have become important phases in the digital design process. In many of the prevailing debugging methods, counterexamples play an immense role. Hence generating fewer and more accurate counterexamples
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1d521b9607b597af4efaab6423a2f6db
https://doi.org/10.1109/ewdts.2013.6673083
https://doi.org/10.1109/ewdts.2013.6673083
Publikováno v:
Asian Test Symposium
Inserting scan chain into the circuit alongside the combinational automatic test pattern generation (ATPG) is the most commonly used test technique for digital circuits. Since power dissipation in test mode is generally much higher than in the functi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f0be68e5677ff9c2539a69377b06d71
https://doi.org/10.1109/ats.2012.38
https://doi.org/10.1109/ats.2012.38