Zobrazeno 1 - 10 of 13 pro vyhledávání: '"Hoosung Cho"'
1
A Fully Performance Compatible 45 nm 4-Gigabit Three Dimensional Double-Stacked Multi-Level NAND Flash Memory With Shared Bit-Line Structure
Autor: Hoosung Cho, Doo-gon Kim, Ki-Tae Park, Yeong-Taek Lee, Hansoo Kim, Soon-Moon Jung, Jae-Hoon Jang, Soonwook Hwang, Myounggon Kang, Youngwook Jeong, Yong-Il Seo, Chang-Hyun Kim
Publikováno v: IEEE Journal of Solid-State Circuits. 44:208-216
A 3-dimensional double stacked 4 gigabit multilevel cell NAND flash memory device with shared bitline structure have successfully developed. The device is fabricated by 45 nm floating-gate CMOS and single-crystal Si layer stacking technologies. To su
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b32f938fde8d4137c27a41345287899c
https://doi.org/10.1109/jssc.2008.2006437
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2
A 45nm 4Gb 3-Dimensional Double-Stacked Multi-Level NAND Flash Memory with Shared Bitline Structure
Autor: Kitae Park, Myounggon Kang, Yeong-Taek Lee, Han-soo Kim, Hoosung Cho, Youngwook Jeong, Soonwook Hwang, Yong-ll Seo, Jae-Hoon Jang, Won-Seong Lee, Chang-Hyun Kim, Doo-gon Kim, Soon-Moon Jung
Publikováno v: ISSCC
Recently, 3-dimensional (3D) memories have regained attention as a potential future memory solution featuring low cost, high density and high performance. We present a 3D double stacked 4Gb MLC NAND flash memory device with shared bitline structure,
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2968e55b5c5d0e4823abfa1d8dd4231e
https://doi.org/10.1109/isscc.2008.4523281
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3
Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node
Autor: Jong-Hyuk Kim, Soon-Moon Jung, Young-Seop Rah, Wonseok Cho, Kinam Kim, Jae-Hun Jeong, Kyoung-Hon Kim, Hoosung Cho, Yang-Soo Son, Jun-Beom Park, Jae-Hoon Jang, Min-Sung Song, Young-Chul Chang, Jin-Soo Lim
Publikováno v: 2006 International Electron Devices Meeting.
For the first time, the 3 dimensionally stacked NAND Flash memory, is developed by implementing S3 (Single-crystal Si layer Stacking ) technology, which was used to develop S3 SRAM previously. The NAND cell arrays are formed on the ILD as well as on
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::d84ae67d7d3efdc0dfab1b0c8774a7a5
https://doi.org/10.1109/iedm.2006.346902
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4
65nm high performance SRAM technology with 25F/sup 2/, 0.16um/sup 2/ S/sup 3/ (stacked single-crystal Si) SRAM cell, and stacked peripheral SSTFT for ultra high density and high speed applications
Autor: C.Y. Chang, Wonsuk Cho, Tae-Hong Ha, Bonghyun Choi, Kinam Kim, Hoon Lim, Jai-kyun Park, Soon-Moon Jung, Hoosung Cho, Jae-Hun Jeong, Han-Byung Park, Byoungkeun Son, Young-Seop Rah
Publikováno v: Proceedings of 35th European Solid-State Device Research Conference, 2005. ESSDERC 2005..
For the first time, the 65nm high performance transistor technology and the highly compacted double stacked S/sup 3/ SRAM cell with a size of 25F/sup 2/, and 0.16/spl mu/m/sup 2/ has been combined for providing the high density and high density solut
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::13e9b4699d38e9e611d6431ab3ac9e47
https://doi.org/10.1109/essder.2005.1546707
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5
Highly cost effective and high performance 65nm S/sup 3/ ( stacked single-crystal Si) SRAM technology with 25f 2 , 0.16μm/sup 2/ cell and doubly stacked SSTFT cell transistors for ultra high density and high speed applications
Autor: C.Y. Chang, Bonghyun Choi, Hoosung Cho, Hoon Lim, Han-Byung Park, Byoungkeun Son, Jongho Yun, Wonsuk Cho, Tae-Hong Ha, Seung-Chul Lee, Young-Seop Rah, Jae-Hun Jeong, Jae-Hoon Jang, Kinam Kim, Jai-kyun Park, Soon-Moon Jung
Publikováno v: Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..
In order to meet the great demands for higher density SRAM in all area of SRAM applications, the 25F/sup 2/S/sup 3/ (stacked single-crystal Si ) SRAM cell, which is a truly 3-dimensional device by stacking the load PMOS and the pass NMOS Tr. on the p
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b43a830ec3802193ec30ae5cc91eb6bd
https://doi.org/10.1109/.2005.1469275
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6
Highly area efficient and cost effective double stacked S/sup 3/(stacked single-crystal Si) peripheral CMOS SSTFT and SRAM cell technology for 512M bit density SRAM
Autor: Jae-Hoon Jang, Byung-Il Ryu, Hoosung Cho, Sung-Jin Kim, Kinam Kim, Jonghoon Na, Bonghyun Choi, Chadong Yeo, Yongha Kang, Dae-Gi Bae, Young-Chul Chang, Kun-Ho Kwak, Soon-Moon Jung, Jae-Hun Jeong, Hoon Lim, Jong-Hyuk Kim, Wonseok Cho
Publikováno v: IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..
For the first time, the highest density SRAM, such as 512M bit SRAM, is developed by implementing the smallest 25F/sup 2/S/sup 3/ SRAM cell technology, whose cell size is 0.16/spl mu/m/sup 2/, and area saving peripheral SSTFT (stacked single-crystal
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::7150ac74da5f9f23c1a9b566f0746441
https://doi.org/10.1109/iedm.2004.1419128
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8
Soft error immune 0.46 μm/sup 2/ SRAM cell with MIM node capacitor by 65 nm CMOS technology for ultra high speed SRAM
Autor: Hoosung Cho, Byoungkeun Son, Wonseok Cho, Hoon Lim, Jae-Hun Jeong, Sug-Woo Jung, Soon-Moon Jung, Kinam Kim, Han-Byung Park, Hatae Hong, Young-Chul Jang
Publikováno v: IEEE International Electron Devices Meeting 2003.
The smallest SRAM cell, 0.46 um/sup 2/, is realized by a single pitch cell layout, gate poly trim mask technique, 80 nm contact holes formed by polymer attaching process, and a 193 nm ArF lithography process. The MIM (metal-insulator-metal) node capa
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::8bebd49ec02afb189b6a0aed581372e5
https://doi.org/10.1109/iedm.2003.1269281
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