Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Hoonsang Jin"'
Publikováno v:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems. 29:1271-1284
Satisfiability (SAT) solvers often benefit from transformations of the formula to be decided that allow them to do more through deduction and decrease their reliance on enumeration. For formulae in conjunctive normal form, subsumed clauses may be rem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::045d5d9c20f454b63ec7e441094b2964
https://doi.org/10.1109/tcad.2010.2049135
https://doi.org/10.1109/tcad.2010.2049135
Publikováno v:
Journal on Satisfiability, Boolean Modeling and Computation. 3:47-66
The last few years have seen the advent of a new breed of decision procedures for various fragments of rst-order logic based on propositional abstraction. A lazy satisabilit y checker for a given fragment of rst-order logic invokes a theory-specic de
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d6030317cf38e5ae100d84ed6462dec9
https://doi.org/10.3233/sat190029
https://doi.org/10.3233/sat190029
Autor:
Hoonsang Jin, Fabio Somenzi
Publikováno v:
Electronic Notes in Theoretical Computer Science. 119:51-65
In Bounded Model Checking (BMC), the search for counterexamples of increasing lengths is translated into a sequence of satisfiability (SAT) checks. It is natural to try to exploit the similarity of these SAT instances by forwarding clauses learned du
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::9f8cd72fb64ab1f5907528891533677d
https://doi.org/10.1016/j.entcs.2004.06.062
https://doi.org/10.1016/j.entcs.2004.06.062
Publikováno v:
TACAS
The ability to generate counterexamples for failing properties is often cited as one of the strengths of model checking. However, it is often difficult to interpret long error traces in which many variables appear. Besides, a traditional error trace
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::25f9130724aab7d53a5d32ee952b210f
https://doi.org/10.1007/s10009-004-0146-9
https://doi.org/10.1007/s10009-004-0146-9
Publikováno v:
DATE
Satisfiability (SAT) solvers often benefit from clauses learned by the DPLL procedure, even though they are by definition redundant. In addition to those derived from conflicts, the clauses learned by dominator analysis during the deduction procedure
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b68f2d9648a66574ba11551a618afe15
https://doi.org/10.1109/date.2011.5763033
https://doi.org/10.1109/date.2011.5763033
Publikováno v:
Lecture Notes in Computer Science ISBN: 9783642027765
SAT
SAT
This paper describes how term-if-then-else (term-ITE ) is handled in Satisfiability Modulo Theories (SMT) and to decide Linear Arithmetic Logic (LA ) in particular. Term-ITEs allow one to conveniently express verification conditions; hence, they are
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::5b60196d0e6fa616186fbebc5d6c9e61
https://doi.org/10.1007/978-3-642-02777-2_20
https://doi.org/10.1007/978-3-642-02777-2_20
Autor:
Petr William Spacek, Fabio Somenzi, Bob Kurshan, Kavita Ravi, Hyondeuk Kim, John LeRoy Pierce, Hoonsang Jin
Publikováno v:
Computer Aided Verification ISBN: 9783540705437
CAV
CAV
Constrained random simulation is supported by constraint solvers integrated within simulators. These constraint solvers need to be fast and memory efficient to maintain simulation performance. Binary Decision Diagrams (BDDs) have been successfully ap
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bfe1c6710e7cbc1818beb1c903478a09
https://doi.org/10.1007/978-3-540-70545-1_46
https://doi.org/10.1007/978-3-540-70545-1_46
Autor:
Jang-Hwan Kim, Sungjoo Yoo, Jeong-Taek Kong, Jeong Eun Kim, Kyu-Myung Choi, Sangwoo Lee, Bum-Seok Yoo, Hye-Jeong Nam, Soo-Kwan Eo, Hoonsang Jin, Shea-yun Lee, Dong-Hyun Song, Jaehyung Hwang, Sungpack Hong
Publikováno v:
CODES+ISSS
Virtual platform (ViP), or ESL (Electronic System Level) simulation model, is one of the most widely renowned system level design techniques. In this paper, we present a case study of creating and applying the ViP in the development of a new hard dis
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::afb983650f1dc83e3af367c3b27a94be
https://doi.org/10.1145/1176254.1176311
https://doi.org/10.1145/1176254.1176311
Autor:
Fabio Somenzi, Hoonsang Jin
Publikováno v:
DATE
We present a new approach to conflict analysis for propositional satisfiability solvers based on the DPLL procedure and clause recording. When conditions warrant it, we generate a supplemental clause from a conflict. This clause does not contain a un
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::91b9d56174a15696f6443ed757a9d169
https://doi.org/10.1109/date.2006.244149
https://doi.org/10.1109/date.2006.244149
Autor:
null HoonSang Jin, F. Somenzi
Publikováno v:
Proceedings. 42nd Design Automation Conference, 2005..
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4bfbcbed2de93b052a692061517db6b4
https://doi.org/10.1109/dac.2005.193911
https://doi.org/10.1109/dac.2005.193911