Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Honglong Luo"'
Publikováno v:
AIP Advances, Vol 7, Iss 9, Pp 095320-095320-10 (2017)
Three-dimensional (3D) integration technology using Cu interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices. However, Cu diffuses into SiO2 and requires a barrier layer such as Ta to ensur
Externí odkaz:
https://doaj.org/article/7fa8dd3f0c064032a7a66896711b2aed
Publikováno v:
2017 18th International Conference on Electronic Packaging Technology (ICEPT).
Integrated circuits (ICs) undergo dimensional reduction and the functional unit of density dramatically increases, the reliability issue becomes more critical, especially with respect to three-dimensional (3D) silicon integration technology. Through-
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d3da65969965c8c29ee8720955164017
https://doi.org/10.1109/icept.2017.8046687
https://doi.org/10.1109/icept.2017.8046687
Publikováno v:
2017 18th International Conference on Electronic Packaging Technology (ICEPT).
In this paper, a chip level stacked module, 100-µm pitch chip on chip (CoC) interconnection with Cu/Sn/Cu microbumps, was assembled by thermal compression bonding process. Daisy chain circuit in the package is electrically connected to high speed Da
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::aa97440051b0cbae1647a15046ba9564
https://doi.org/10.1109/icept.2017.8046692
https://doi.org/10.1109/icept.2017.8046692
Publikováno v:
2016 17th International Conference on Electronic Packaging Technology (ICEPT).
Through Silicon Via(TSVs) technology is one of the most prominent feature in future microelectronic devices packaging. Since TSVs contain the interfaces of heterogeneous materials that have high CTE mismatch, and would hence produce large thermal str
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f3f38a19658c5c15d7c3925b2507033f
https://doi.org/10.1109/icept.2016.7583372
https://doi.org/10.1109/icept.2016.7583372
Publikováno v:
AIP Advances, Vol 7, Iss 9, Pp 095320-095320-10 (2017)
Three-dimensional (3D) integration technology using Cu interconnections has emerged as a promising solution to improve the performance of silicon microelectronic devices. However, Cu diffuses into SiO2 and requires a barrier layer such as Ta to ensur
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::99d64a6e7ccdbc181f6603275e62f372
https://doaj.org/article/7fa8dd3f0c064032a7a66896711b2aed
https://doaj.org/article/7fa8dd3f0c064032a7a66896711b2aed