Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Hong Keun Ahn"'
Publikováno v:
IEEE Access, Vol 8, Pp 187754-187765 (2020)
The convolutional neural network (CNN)-based super-resolution (SR) has shown outstanding performance in the field of computer vision. The implementation of inference hardware for CNN-based SR has suffered from the intensive computation with severely
Externí odkaz:
https://doaj.org/article/5763f797fe0447f9a6df06fdc9748e65
Autor:
Sumin Lee, Ki-Beom Lee, Sunghwan Joo, Hong Keun Ahn, Junghyup Lee, Dohyung Kim, Bumsub Ham, Seong-Ook Jung
Publikováno v:
ESSCIRC 2022- IEEE 48th European Solid State Circuits Conference (ESSCIRC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::29200b205e53140a12255647d4b71dd9
https://doi.org/10.1109/esscirc55480.2022.9911509
https://doi.org/10.1109/esscirc55480.2022.9911509
Publikováno v:
IEEE Transactions on Circuits and Systems I: Regular Papers. 68:2481-2493
Essential design requirements for a sense amplifier (SA) used in the resistance monitoring write termination (RM-WT) scheme are suggested to reduce the write energy of spin-transfer-torque random access memory (STT-RAM) while achieving a write pass y
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3800a70e9682bdc76602a430338263ac
https://doi.org/10.1109/tcsi.2021.3069710
https://doi.org/10.1109/tcsi.2021.3069710
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:2650-2657
Cross-point-array nonvolatile ternary content-addressable memory (CPA nvTCAM) has recently emerged as an alternative to static random-access-memory-type TCAM, based on increased demands for high-capacity and low-power attributes. The CPA structure ha
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d99c1db586d95b7d48d969e6f7a94d0b
https://doi.org/10.1109/tvlsi.2020.3027254
https://doi.org/10.1109/tvlsi.2020.3027254
Publikováno v:
2021 18th International SoC Design Conference (ISOCC).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9465772d76c540287c09aa76edcbba5e
https://doi.org/10.1109/isocc53507.2021.9614013
https://doi.org/10.1109/isocc53507.2021.9614013
Publikováno v:
2018 International Conference on Electronics, Information, and Communication (ICEIC).
The performance and power of the memory system cannot gradually follow the improving speed and power of the computational cores. To improve the memory performance, the L3 cache implemented with SRAM is generally used. However, the SRAM is not suitabl
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0798bab4f40e64782b5bb04823c32153
https://doi.org/10.23919/elinfocom.2018.8330706
https://doi.org/10.23919/elinfocom.2018.8330706
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Dec2020, Vol. 28 Issue 12, p2650-2657, 8p
Publikováno v:
IEEE Transactions on Circuits & Systems. Part I: Regular Papers; Jun2021, Vol. 68 Issue 6, p2481-2493, 13p
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems; Feb2019, Vol. 27 Issue 2, p387-397, 11p