Zobrazeno 1 - 10
of 10
pro vyhledávání: '"Hokmin Ho"'
Publikováno v:
ECS Transactions. 27:55-60
NMOS narrow width transistor driving current as a function of shallow trench isolation (STI) processes and channel implant conditions were studied on a 65nm CMOS technology. It is found that the magnitude of compressive stress in STI could modulate t
Autor:
Hokmin Ho, Huachun Guo, Allan Zhou, Shuaigong Chen, I. C. Chen, Z.-H. Gan, Jianhua Ju, K. Zheng, Jay Ning, Jinhua Liu, Guiming Wang, Jimmy Wu
Publikováno v:
ECS Transactions. 27:33-38
PMOS poly Si gate blank pre-doping combined with NMOS poly Si counter pre-doping process scheme is demonstrated to keep the benefit of one photolithography saving while no device or product properties degradation.
Autor:
Cathy Ren, Jay Ning, Allan Zhou, Zhaoxu Shen, Eric Liu, Hokmin Ho, Daniel Deng, Susu Wei, Jianhua Ju, Jinhua Liu
Publikováno v:
ECS Transactions. 18:117-122
Three key process steps in shallow trench isolation (STI) technology: STI liner oxide, STI to AA step height, and annealing temperature. Their impacts on NMOS devices leakage, SRAM standby current and Vccmin have been studied. MOSFET transistors off
Autor:
Brisk Wang, Daniel Deng, Hokmin Ho, Zhaoxu Shen, Eric Liu, Jay Ning, Allan Zhou, Jianhua Ju, Shugang Dai, Albert Hung, Jinhua Liu, Julie Tang
Publikováno v:
ECS Transactions. 18:27-31
Spike Rapid Thermal Annealing (RTA) is commonly used method for source and drain dopant activation in 65nm CMOS technology. It is found that the Idsat variation is very sensitive to RTA temperature. To better control the Idsat uniformity across the s
Autor:
Zhaoxu Shen, Hokmin Ho, Eric Liu, Shugang Dai, Ju Jianhua, Jay Ning, Albert Hung, Brisk Wang, Zhou Allan, Jinhua Liu
Publikováno v:
ECS Transactions. 18:15-19
Around 50mV RSCE and SCE improvement has been obtained by C co-implantation optimization in 65nm node CMOS technology. Besides this, gate to source/drain overlap capacitance (Cgd0) and junction capacitance (Cj) are seen to be reduced 6% and 11% respe
Publikováno v:
The Fourth International Workshop on Junction Technology, 2004. IWJT '04..
In this work, CMOS devices with very low leakage current (Ioff) are studied for Ultra Low Power (ULP) applications. The ULP is targeted for worst-case Ioff
Publikováno v:
Fourth International Workshop on Junction Technology, 2004 (IWJT '04); 2004, p328-330, 3p
Autor:
Liu, Jinhua, Allan, Zhou, Jianhua, Ju, Dai, Shugang, Shen, Zhaoxu, Liu, Eric, Wang, Brisk, Hung, Albert, and, Hokmin Ho, Ning, Jay
Publikováno v:
ECS Transactions; March 2009, Vol. 18 Issue: 1 p15-19, 5p
Autor:
Ju, Jianhua, Liu, Eric, Shen, Zhaoxu, Zhou, Allan, Liu, Jinhua, Deng, Daniel, Ren, Cathy, Wei, Susu, and, Hokmin Ho, Ning, Jay
Publikováno v:
ECS Transactions; March 2009, Vol. 18 Issue: 1 p117-122, 6p
Autor:
Ju, Jianhua, Liu, Eric, Dai, Shugang, Zhou, Allan, Shen, Zhaoxu, Liu, Jinhua, Wang, Brisk, Deng, Daniel, Tang, Julie, Hung, Albert, and, Hokmin Ho, Ning, Jay
Publikováno v:
ECS Transactions; March 2009, Vol. 18 Issue: 1 p27-31, 5p