Zobrazeno 1 - 10
of 20
pro vyhledávání: '"Hoe-ju Chung"'
Autor:
Hye-Ran Kim, Chul-Sung Park, Kwang-Il Park, Jin-Il Lee, Young-Chul Cho, Jun-Young Park, Chang-Yong Lee, Hyoung-Joo Kim, Ki-Won Lee, Joo Sun Choi, Seong-Jin Jang, Hoe-ju Chung, Jong-ho Lee, Tae-Young Oh, Yong-Cheol Bae, Seung-Hoon Oh, Young-Ryeol Choi, Su-Yeon Doo, Kyung-Soo Ha, Tae-Seong Jang
Publikováno v:
IEEE Journal of Solid-State Circuits. 50:178-190
A 1.0 V 8 Gbit LPDDR4 SDRAM with 3.2 Gbps/pin speed and integrated ECC engine for sub-1 V DRAM core is presented. DRAM internal read-modify-write operation for data masked write makes the integrated ECC engine possible in a commodity DRAM. Time inter
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b85aa5494f6f90794f6e13df897888c5
https://doi.org/10.1109/jssc.2014.2353799
https://doi.org/10.1109/jssc.2014.2353799
Autor:
Jei-Hwan Yoo, Hoe-ju Chung, Duk-Min Kwon, Woo-Seop Kim, Man-Sik Choi, Dong-Hyun Jang, Sae-Jang Oh, Jaesung Ahn, So-Ra Kim, Jung-Bae Lee, Chang-Hyun Kim, Sooho Cha, Jin-Ho Kim, Seongmoo Heo, Hyun-Kyung Kim, Hoon Lee, Nam-Seog Kim, Jae-Wook Lee, Uk-Song Kang, Han-Sung Joo, Eun-Mi Lee, Keum-Hee Ma, Tae-Kyung Jung, Soon-Hong Ahn
Publikováno v:
ISSCC
An 8 Gb 4-stack 3-D DDR3 DRAM with through-Si-via is presented which overcomes the limits of conventional modules. A master-slave architecture is proposed which decreases the standby and active power by 50 and 25%, respectively. It also increases the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9193e6c785df594cf1c574906e064bb4
https://doi.org/10.1109/jssc.2009.2034408
https://doi.org/10.1109/jssc.2009.2034408
Autor:
Jei-Hwan Yoo, Woo-Seop Kim, Kim Sang-Yun, Hyung-seuk Kim, Jae-Kwan Kim, Soouk Lim, Hoe-ju Chung, Jung-Bae Lee, Moon-Sook Park, Yun-Sang Lee, Jung Sunwoo, Young-don Choi, Hwan-Wook Park, Young-Chan Jang, Chang-Hyun Kim
Publikováno v:
IEEE Journal of Solid-State Circuits. 44:2987-2998
A 1-Gbit DRAM with 5.8-Gb/s/pin unidirectional differential I/Os was implemented by 70 nm DRAM process and a main memory module with dual in-line memory module was assembled. The implemented DRAM chips have control methods for core noise injection an
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::ffa8cfcae6804fc1cf089a3ded51feb2
https://doi.org/10.1109/jssc.2009.2028948
https://doi.org/10.1109/jssc.2009.2028948
Autor:
Jung Sunwoo, Hoon Lee, Woo-Seop Kim, Moon-Sook Park, Kyu-hyoun Kim, Young-Chan Jang, Hoe-ju Chung, Chang-Hyun Kim, Su-Jin Chung, Duk-ha Park, Jae-Kwan Kim, Jin-Young Kim, Hyun-Kyung Kim, Hwan-Wook Park, Uk-Song Kang, Young-Taek Lee, Joo Sun Choi, Kee-Won Kwon, Hyung-seuk Kim
Publikováno v:
ISSCC
This paper proposes a deca-data rate clocking scheme and relevant I/O circuit techniques for a multi-Gb/s/pin memory interface. A deca-data rate scheme transmits 10 bits in one external clock cycle to transfer an error control code along with origina
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::459383a88b892d96879ad94fa0d7818a
https://doi.org/10.1109/jssc.2006.888297
https://doi.org/10.1109/jssc.2006.888297
Autor:
Kyu-hyoun Kim, Hoe-ju Chung, Yun-Sang Lee, Moo-Sung Chae, Jung-Bae Lee, Soo-In Cho, Jae-Kwan Kim, Dae-Hee Jung, Seung-young Seo, Chang-Hyun Kim, Churoo Park, Jin-hyung Cho, Sung-Ho Choi, Jun-Ho Shin, Ki-whan Song, Taek-Seon Park, Jae-Jun Lee, Seung-Hoon Lee
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:831-838
A 1.5-V 512-Mb DDR3 synchronous DRAM prototype was designed and fabricated in 80-nm technology. Critical to the signal integrity in DDR3 point-to-2points (P22P) interfacing is an efficient calibration scheme and C/sub IO/ minimization, which were ach
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8adf14d534c9b22e241d2724ebe5ef45
https://doi.org/10.1109/jssc.2006.870808
https://doi.org/10.1109/jssc.2006.870808
Autor:
Seung-Jun Bae, Jin-Il Lee, Gong-Heum Han, Young-Chul Cho, Su-Yeon Doo, Doo-Hee Hwang, Ki-Won Lee, Chul-Sung Park, Hoe-ju Chung, Jang-Woo Ryu, Joo Sun Choi, Chang-Ho Shin, Jung-Bae Lee, Tae-Young Oh, Joon-Young Park, Changyoung Lee, Min Soo Jang, Hyoung-Joo Kim, Kwang-Il Park, Jung-Bum Shin, Kyung-Soo Ha, Daesik Moon, Tae-Seong Jang, Jae-Woong Lee, Ki-Han Kim, Oh Ki-Seok
Publikováno v:
ISSCC
The recent revolution in handheld computing with high-speed cellular network made mobile processors have multi-cores and powerful 3D graphic engines that support FHD (1920×1080) or even higher resolutions. Consequently, the memory bandwidth requirem
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c9290d1d68fcad2afd51d8078cddaebc
https://doi.org/10.1109/isscc.2014.6757500
https://doi.org/10.1109/isscc.2014.6757500
Autor:
Jun-Ho Shin, Su-Jin Ahn, Yeong-Taek Lee, Han-Sung Joo, Jung Sunwoo, Jei-Hwan Yoo, Hoe-ju Chung, Yong-Jin Kwon, Jaehwan Kim, Beakhyoung Cho, Jae-Wook Lee, Chang-Soo Lee, Yong-Jun Lee, Mu-Hui Park, Gitae Jeong, Sang-Hoan Chang, Jin-Young Kim, Soehee Kim, Mingu Kang, Duckmin Kwon, Young-Hoon Oh, Kwang-Jin Lee, Qi Wang, Young-don Choi, Yoohwan Rho, Jae-Yun Lee, Ickhyun Song, Hideki Horii, Sooho Cha, Ki-Sung Kim
Publikováno v:
ISSCC
Phase-change random access memory (PRAM) is considered as one of the most promising candidates for future memories because of its good scalability and cost-effectiveness [1]. Besides implementations with standard interfaces like NOR flash or LPDDR2-N
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9f5ac863917e36ad25b5701fc52bcd26
https://doi.org/10.1109/isscc.2012.6176872
https://doi.org/10.1109/isscc.2012.6176872
Autor:
Sung-Hoon Kim, Yong-Jun Lee, Byung-Hoon Jeong, Sang-Tae Kim, Jung Sunwoo, HoGeun Cho, Jin-Young Kim, Sunghyun Jun, Inchul Shin, Hoe-ju Chung, Woo-Yeong Cho, Jae-Wook Lee, Woochul Jun, Jun-Ho Shin, Joon-Min Park, Chang-han Choi, Qi Wang, Young-don Choi, Young-Hyun Jun, Ki-whan Song, Byung-Jun Min, KiSeung Kim, Jei-Hwan Yoo, Mu-Hui Park, Yoohwan Rho, Won-Ryul Chung, Seok-Won Hwang, Sang-whan Chang, Ickhyun Song, Ki-won Lim, Beak-Hyung Cho, Kwang-Jin Lee, Sooho Cha, Jaewhan Kim, Duk-Min Kwon
Publikováno v:
ISSCC
In mobile systems, the demand for the energy saving continues to require a low power memory sub-system. During the last decade, the floating-gate flash memory has been an indispensable low power memory solution. However, NOR flash memory has begun to
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f1f97aa243d95e0484bd2bb05761a837
https://doi.org/10.1109/isscc.2011.5746415
https://doi.org/10.1109/isscc.2011.5746415
Autor:
null Uksong Kang, null Hoe-Ju Chung, null Seongmoo Heo, null Soon-Hong Ahn, null Hoon Lee, null Soo-Ho Cha, null Jaesung Ahn, null DukMin Kwon, null Jin Ho Kim, null Jae-Wook Lee, null Han-Sung Joo, null Woo-Seop Kim, null Hyun-Kyung Kim, null Eun-Mi Lee, null So-Ra Kim, null Keum-Hee Ma, null Dong-Hyun Jang, null Nam-Seog Kim, null Man-Sik Choi, null Sae-Jang Oh, null Jung-Bae Lee, null Tae-Kyung Jung, null Jei-Hwan Yoo, null Changhyun Kim
Publikováno v:
2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b7e4f34a5587145c53db725a6a887012
https://doi.org/10.1109/isscc.2009.4977342
https://doi.org/10.1109/isscc.2009.4977342
Autor:
Jung-Bae Lee, Sang-Yun Kim, Jung Sunwoo, Eun-Mi Lee, Young-Chan Jang, Woo-Seop Kim, Hwan-Wook Park, Hyun-Kyung Kim, Hoe-ju Chung, Young-Ju Kim, Su-Jin Chung, Chang-Hyun Kim, Soouk Lim, Yun-Sang Lee, Young-don Choi, Moon-Sook Park, Jae-Kwan Kim, Hyungwsuk Kim
Publikováno v:
2008 IEEE Asian Solid-State Circuits Conference.
A 5.8 Gb/s/pin DRAM with unidirectional differential I/Os and 1 Gbit memory core was designed and 23.2 GB/s memory module was assembled. Tx BER measurement on an electrical test board similar to real memory sub-systempsilas environment was performed
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::017af6aeeeb40aef38e73941d251a388
https://doi.org/10.1109/asscc.2008.4708721
https://doi.org/10.1109/asscc.2008.4708721