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of 8
pro vyhledávání: '"Ho-Ren Chuang"'
Autor:
Ho-ren Chuang, 莊賀任
102
IC (Integrated Circuit) chip marking inspection is one of the critical steps during the IC manufacture process. Through the examination of the marks on the IC chip, the correctness of IC orientation can be assured. In this paper, we present
IC (Integrated Circuit) chip marking inspection is one of the critical steps during the IC manufacture process. Through the examination of the marks on the IC chip, the correctness of IC orientation can be assured. In this paper, we present
Externí odkaz:
http://ndltd.ncl.edu.tw/handle/88850267986544912370
Autor:
Ho-Ren Chuang, Karim Manaouil, Tong Xing, Antonio Barbalace, Pierre Olivier, Balvansh Heerekar, Binoy Ravindran
Publikováno v:
Chuang, H-R, Manaouil, K, Xing, T, Barbalace, A, Olivier, P, Heerekar, B & Ravindran, B 2023, Aggregate VM: Why Reduce or Evict VM’s Resources When You Can Borrow Them From Other Nodes? in EuroSys '23: Proceedings of the Eighteenth European Conference on Computer Systems . EuroSys: European Conference on Computer Systems, Association for Computing Machinery (ACM), New York, pp. 469-487, EuroSys '23: Eighteenth European Conference on Computer Systems, Rome, Italy, 8/05/23 . https://doi.org/10.1145/3552326.3587452
Hardware resource fragmentation is a common issue in data centers. Traditional solutions based on migration or overcommitment are unacceptably slow, and modern commercial or research solutions like Spot VM may reduce or evict VM’s resources anytime
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::43da9c0034e8d7086f7fa29c0782e1d8
https://www.pure.ed.ac.uk/ws/files/339440790/Aggregate_VM_CHUANG_DOA18012023_AFV_CC_BY.pdf
https://www.pure.ed.ac.uk/ws/files/339440790/Aggregate_VM_CHUANG_DOA18012023_AFV_CC_BY.pdf
Autor:
Naarayanan Rao VSathish, Ho-Ren Chuang, Edson Horta, Cesar Philippidis, Pierre Olivier, Binoy Ravindran, Antonio Barbalace
Publikováno v:
Horta, E, Chuang, H-R, VSathish, N R, Philippidis, C, Barbalace, A, Olivier, P & Ravindran, B 2021, Xar-Trek: Run-Time Execution Migration among FPGAs and Heterogeneous-ISA CPUs . in Proceedings of the 22nd International Middleware Conference . New York, NY, USA, pp. 104–118, 22nd International Middleware Conference 2021, 6/12/21 . https://doi.org/10.1145/3464298.3493388
Datacenter servers are increasingly heterogeneous: from x86 host CPUs, to ARM or RISC-V CPUs in NICs/SSDs, to FPGAs. Previous works have demonstrated that migrating application execution at run-time across heterogeneous-ISA CPUs can yield significant
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::0f09c365c1e2a18381b26c0761fe40e7
https://doi.org/10.1145/3464298.3493388
https://doi.org/10.1145/3464298.3493388
Publikováno v:
ICDCS
Increasing the computing performance within a single-machine form factor is becoming increasingly difficult due to the complexities in scaling processor interconnects and coherence protocols. On the other hand, converting existing applications to run
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::28c697e291a33170bd0f481bba9cde45
https://doi.org/10.1109/icdcs47774.2020.00021
https://doi.org/10.1109/icdcs47774.2020.00021
Publikováno v:
SYSTOR
Due to the slowdown of Moore's Law, systems designers have begun integrating non-cache-coherent heterogeneous computing elements in order to continue scaling performance. Programming such systems has traditionally been difficult - developers were for
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::556079b823a7b39a3ced967e516ec306
https://doi.org/10.1145/3383669.3398278
https://doi.org/10.1145/3383669.3398278
Autor:
Anthony Carno, Vincent Legout, Binoy Ravindran, Ho-Ren Chuang, Antonio Barbalace, Robert Lyerly, Christopher Jelesnianski
Publikováno v:
ASPLOS
Energy efficiency is one of the most important design considerations in running modern datacenters. Datacenter operating systems rely on software techniques such as execution migration to achieve energy efficiency across pools of machines. Execution
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::14f5ab8183fac11a12b9a01072779747
https://doi.org/10.1145/3093315.3037738
https://doi.org/10.1145/3093315.3037738
Publikováno v:
ICDCS
As the number of processors and the size of the memory of computing systems keep increasing, the likelihood of CPU core failures, memory errors, and bus failures increases and can threaten system availability. Software components can be hardened agai
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4ed353f0cc642e780d371e8f1485af7
https://doi.org/10.1109/icdcs.2017.140
https://doi.org/10.1109/icdcs.2017.140
Publikováno v:
ICDCS
With the advances in network speeds a single processor cannot cope anymore with the growing number of data streams from a single network card. Multicore processors come at a rescue but traditional SMP OSes, which integrate the software network stack,
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9ffeab52ef6a8a0c89bdb47f80e5976e
https://doi.org/10.1109/icdcs.2017.90
https://doi.org/10.1109/icdcs.2017.90