Zobrazeno 1 - 6
of 6
pro vyhledávání: '"Hisayuki Nishimura"'
Performance and reliability improvements in poly-Si TFT's by fluorine implantation into gate poly-Si
Autor:
Takashi Ipposhi, M. Ashida, S. Maeda, Hisayuki Nishimura, Shigeto Maegawa, Y. Inoue, O. Tanina, T. Ichiki, T. Nishimura, Natsuro Tsubouchi
Publikováno v:
IEEE Transactions on Electron Devices. 42:1106-1112
High-performance and high-reliability TFT's have been obtained using a fluorine ion implantation technique. The fluorine implantation into the gate poly-Si of TFT caused a positive Vth shift, increased the ON current, and decreased the leakage curren
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c2dd4505c7fb136e67079a1c249ce938
https://doi.org/10.1109/16.387244
https://doi.org/10.1109/16.387244
Autor:
Hisayuki Nishimura, Takashi Ipposhi, O. Tanina, Y. Inoue, S. Maeda, Shigeto Maegawa, Hirotada Kuriyama, T. Nishimura
Publikováno v:
IEEE Transactions on Electron Devices. 42:2117-2123
We propose a vertical /spl Phi/-shape transistor (V/spl Phi/T) cell for 1 Gbit DRAM and beyond. The V/spl Phi/T is a vertical MOSFET whose gate surrounds its channel region like a Greek-alphabetic letter /spl Phi/, fabricated through the penetration
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::97c85db912cb92109819bf6c7e4a61c7
https://doi.org/10.1109/16.477769
https://doi.org/10.1109/16.477769
Autor:
T. Muragishi, Tadashi Nishimura, Hisayuki Nishimura, T. Ipposhi, J. Mitsuhashi, S. Maegawa, T. Ichiki, Yasuo Inoue, S. Maeda, M. Ashida
Publikováno v:
Journal of Applied Physics. 76:8160-8166
It is found that 0.1 V‐order threshold voltage shift (Vth shift) takes place in polycrystalline‐silicon thin film transistors during negative‐bias temperature stress (−BT stress), while the Vth shift in the case of positive‐bias temperature
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8812295bd0f6c8d081a1af2fe11dc58f
https://doi.org/10.1063/1.358430
https://doi.org/10.1063/1.358430
Autor:
S. Maeda, Natsuro Tsubouchi, O. Tanina, M. Ashida, Hisayuki Nishimura, T. Ichiki, T. Ipposhi, Y. Inoue, T. Nishimura, Shigeto Maegawa
Publikováno v:
Proceedings of IEEE International Electron Devices Meeting.
High-performance and high-reliability TFTs were obtained using a fluorine ion implantation (FII) technique. The FII into the TFT gate poly-Si caused a positive Vth shift, increased the on current and decreased the leakage current significantly. Our i
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e139e182ccae810884c7588e14e86cb2
https://doi.org/10.1109/iedm.1993.347403
https://doi.org/10.1109/iedm.1993.347403
Autor:
Natsuro Tsubouchi, Shigenobu Maeda, O. Tanina, Hirotada Kuriyama, Y. Inoue, Takashi Ipposhi, Shigeto Maegawa, Hisayuki Nishimura
Publikováno v:
Extended Abstracts of the 1994 International Conference on Solid State Devices and Materials.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f4f777f03fb873d92dd5cbba7862bf97
https://doi.org/10.7567/ssdm.1994.a-12-2
https://doi.org/10.7567/ssdm.1994.a-12-2
Autor:
Hirotada Kuriyama, Osamu Tanina, Shigeto Maegawa, Hisayuki Nishimura, Shigenobu Maeda, Takashi Ipposhi, Natsuro Tsubouchi, Tadashi Nishimura, Yasuo Inoue
Publikováno v:
Japanese Journal of Applied Physics. 34:895
We propose a novel thin-film-transistor (TFT) structure named gate-all-around TFT (GAT). Its fabrication process is very simple, in that we realize the gate-all-around structure using only a dummy nitride pattern. The GAT shows high channel conductan
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::9dd400efa7146b55795170ad89f162fd
https://doi.org/10.1143/jjap.34.895
https://doi.org/10.1143/jjap.34.895