Zobrazeno 1 - 9
of 9
pro vyhledávání: '"Hisanori Fujisawa"'
Autor:
Haruka NAKAMURA, Yoshimasa TAWATSUJI, Tatsunori MATSUI, Makoto NAKAMURA, Koichi KIMURA, Hisanori FUJISAWA
Publikováno v:
IEICE Transactions on Information and Systems. :1969-1983
Autor:
Fan Mo, Koichi Kimura, Makoto Nakamura, Masafumi Ohtsuka, Hisanori Fujisawa, Shun Morisawa, Huida Jiao, Hayato Yamana
Publikováno v:
ICEIS (1)
Autor:
Huida Jiao, Shun Morisawa, Masafumi Ohtsuka, Hayato Yamana, Koichi Kimura, Fan Mo, Makoto Nakamura, Hisanori Fujisawa
Publikováno v:
IEEE BigData
Online advertising is widely used by commercial companies to attract customers. Tuning advertisement delivery to achieve a high conversion rate (CVR) is crucial for improving advertising effectiveness. Because advertisers require demandside platforms
Publikováno v:
ISLPED
Low power techniques such as clock gating and dynamic frequency scaling cause a sudden surge in power supply current. To reduce the voltage droop induced by such a surge in the load current of an LDO regulator, we propose output voltage boost and ada
Publikováno v:
2009 IEEE Asian Solid-State Circuits Conference.
In this paper, a tailbiting block-interleaved pipelining (BIP) architecture is proposed for high-throughput and energy efficient WiMAX turbo decoders. Conventional sliding window (SW) BIP turbo decoders suffer from many warm-up calculations and large
Autor:
Iwao Sugiyama, Teruo Ishihara, Hideki Yoshizawa, Yuki Sakai, Seiichi Nishijima, Miyoshi Saito, Yoshio Hirose, Naoki Odate, Hisanori Fujisawa, Katsuhiro Yoda
Publikováno v:
2006 IEEE Asian Solid-State Circuits Conference.
Software defined radio (SDR) is expected to be a progressive technology for wireless communications under multi-communication systems. SDR requires high performance, low power consumption, and short latency hardware. We have developed a single-chip b
Publikováno v:
FPT
A new reconfiguration technique for pipelined applications on coarse-grain reconfigurable circuits, the cyclic reconfiguration method, is proposed. In this method, the configurations that have interleaved pipeline stages are switched once per clock.
Akademický článek
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.
Conference
Tento výsledek nelze pro nepřihlášené uživatele zobrazit.
K zobrazení výsledku je třeba se přihlásit.
K zobrazení výsledku je třeba se přihlásit.