Zobrazeno 1 - 10 of 95 pro vyhledávání: '"Hiroyuki Yotsuyanagi"'
4
Open Defect Detection in Assembled Circuit Boards With Built-In Relaxation Oscillators
Autor: Hiroyuki Yotsuyanagi, Yutaka Uematsu, Fumiya Sako, Yasuhiro Ikeda, Masaki Hashizume, Yuki Ikiri, Toru Yazaki, Shyue-Kung Lu
Publikováno v: IEEE Transactions on Components, Packaging and Manufacturing Technology. 11:931-943
In this article, we propose two kinds of electrical interconnect test methods for production tests and field ones of assembled circuit boards, which are performed prior to and after shipping to market, respectively. For these tests, we also propose a
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4290041f8eec81e9cda8f0f6c20d3358
https://doi.org/10.1109/tcpmt.2021.3079159
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5
Fault-Aware Dependability Enhancement Techniques for Flash Memories
Autor: Chi-Tien Sun, Chun-Lung Hsu, Hiroyuki Yotsuyanagi, Masaki Hashizume, Shu-Chi Yu, Shyue-Kung Lu
Publikováno v: IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 28:634-645
By analyzing the fault behaviors of conventional flash memory fault models, two new concise fault types are proposed: the 1-safe fault and the 0-safe fault. For a 1(0)-safe fault, if logic 1(0) is programmed into the faulty cell, the effect of the fa
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b7525568d33189a53d128e491943d75b
https://doi.org/10.1109/tvlsi.2019.2957830
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6
Detectable Resistance Increase of Open Defects in Assembled PCBs by Quiescent Currents through Embedded Diodes
Autor: Masaki Hashizume, Shyue-Kung Lu, Yuya Okumoto, Hiroyuki Yotsuyanagi
Publikováno v: 2021 International Conference on Electronics Packaging (ICEP).
It is discussed in this paper what resistance increase can be detected by an electrical interconnect test method that occurs after shipping to market at interconnects between ICs and printed circuit boards. The test method is based on a quiescent cur
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::5407fb8acd48a2bea8d4985188a24bf7
https://doi.org/10.23919/icep51988.2021.9451913
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10
On Delay Elements in Boundary Scan Cells for Delay Testing of 3D IC Interconnection
Autor: Masaki Hashizume, Toshiaki Satoh, Hiroyuki Yotsuyanagi
Publikováno v: 3DIC
For testing delay faults in 3D IC interconnection, we have proposed a DFT (Design-for- Testability) method for TSVs using a modified boundary scan circuit with embedded Time-to-Digital Converter (TDCBS). A TDCBS cell has a delay element to form a del
Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::ddf991588c2ccf5748aa6301659244d7
https://doi.org/10.1109/3dic48104.2019.9058908
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