Zobrazeno 1 - 10
of 90
pro vyhledávání: '"Hiroo Masuda"'
Autor:
Akihiro Kosoku, MD, PhD, Tomoaki Iwai, MD, PhD, Hiroo Masuda, MD, Kazuya Kabei, MD, PhD, Shunji Nishide, MD, PhD, Keiko Maeda, MSN, Yuki Yoshikawa, PhD, Yasutaka Nakamura, PhD, Sabina De Geest, PhD, Junji Uchida, MD, PhD
Publikováno v:
Transplantation Direct, Vol 9, Iss 3, p e1457 (2023)
Background. A valid and reliable instrument that can measure adherence is needed to identify nonadherent patients and to improve adherence. However, there is no validated Japanese self-report instrument to evaluate adherence to immunosuppressive medi
Externí odkaz:
https://doaj.org/article/6601fa87aede4966ba31e0e09b387ef0
Autor:
Katsuhiro Furukawa, Masanori Hashimoto, Hiroo Masuda, Hidenari Nakashima, Tsuyoshi Sakata, Hiroshi Takafuji, Takashi Sato, Masakazu Tanaka, Koutaro Hachiya, Takaaki Okumura, Toshiki Kanamoto, Atsushi Kurokawa
Publikováno v:
IEICE Transactions on Electronics. :388-392
This paper evaluates impact of self-heating in wire interconnection on signal propagation delay in an upcoming 32nm process technology, using practical physical parameters. This paper examines a 64-bit data transmission model as one of the most heati
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45382aeb3e2d21f8e28eddfb76826b90
https://doi.org/10.1587/transele.e93.c.388
https://doi.org/10.1587/transele.e93.c.388
Autor:
Nobuhiko Goto, Takashi Saito, Hiroo Masuda, Hitoshi Sugihara, Toshiki Kanamoto, Saiko Kobayashi, Takao Sato
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1605-1611
We have developed a macro model, which allows us to describe precise LDMOS DC/AC characteristics. Characterization of anomalous gate input capacitance is the key issue in the LDMOS model development. We have newly employed a T-type distributed RC sch
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdbcbbfa5c302339f13fa7552098445a
https://doi.org/10.1587/transfun.e93.a.1605
https://doi.org/10.1587/transfun.e93.a.1605
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :966-975
A new analog mismatch model in circuit level has been developed. MOS transistor's small signal parameters are modeled in term of their matching character for both strong- and weak-inversion operations. Mismatch analysis on basic CMOS amplifiers are c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0daca05ae67f6e81571afa9267b6e766
https://doi.org/10.1587/transfun.e92.a.966
https://doi.org/10.1587/transfun.e92.a.966
Autor:
Takashi Sato, Hiroo Masuda, Tsuyoshi Sakata, Takaaki Okumura, Toshiki Kanamoto, Nobuto Ono, Hidenari Nakashima, Masanori Hashimoto, Atsushi Kurokawa, Hiroshi Takafuji
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :990-997
SUMMARY Process variation is becoming a primal concern in timing closure of LSI (Large Scale Integrated Circuit) with the progress of process technology scaling. To overcome this problem, SSTA (Statistical Static Timing Analysis) has been intensively
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::801907e091e541b52a368d0907346707
https://doi.org/10.1587/transfun.e92.a.990
https://doi.org/10.1587/transfun.e92.a.990
Autor:
Masakazu Tanaka, Koutaro Hachiya, Atsushi Kurokawa, Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Masanori Hashimoto, Hidenari Nakashima, Tsuyoshi Sakata, Hiroshi Takafuji, Hiroo Masuda, Takashi Sato
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :3016-3023
Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate del
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d1f05e2f488d30fabce6e1e9e63e6fbd
https://doi.org/10.1587/transfun.e92.a.3016
https://doi.org/10.1587/transfun.e92.a.3016
Publikováno v:
IEICE Transactions on Electronics. :647-654
Random variations in Id-Vg characteristics of MOS transistors in an LSI chip are shown to be concisely characterized by using only 3 transistor parameters (Vth, β0, υSAT) in the MOS level 3 SPICE model. Statistical analyses of the transistor parame
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::fdbcf3b887ddd19bd675a9c587104000
https://doi.org/10.1093/ietele/e91-c.4.647
https://doi.org/10.1093/ietele/e91-c.4.647
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1062-1070
We have proposed a random curved surface model as a new mathematical concept which enables the expression of spatial correlation. The model gives us an appropriate methodology to deal with the systematic components of device variation in an LSI chip.
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::988023f1f899d87f7f51da7ba41b8feb
https://doi.org/10.1093/ietfec/e91-a.4.1062
https://doi.org/10.1093/ietfec/e91-a.4.1062
Autor:
Zhangcai Huang, Hiroo Masuda, Akira Kasebe, Atsushi Kurokawa, Toshinori Inoshita, Junko Fujii, Yasuaki Inoue
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :856-864
In general, a corner model with best- and worst-case delay conditions is used in static timing analysis (STA). The best- and worst-case delays of a stage are defined as the fastest and slowest delays from a cell input to the next cell input. In this
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::39044287be5647a3e1bdd9ec44a8a950
https://doi.org/10.1093/ietfec/e89-a.4.856
https://doi.org/10.1093/ietfec/e89-a.4.856
Autor:
Yasuaki Inoue, Yun Yang, Toshiki Kanamoto, Hiroo Masuda, Zhangcai Huang, Akira Kasebe, Atsushi Kurokawa
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :847-855
In advanced ASIC/SoC physical designs, interconnect parasitic extraction is one of the important factors to determine the accuracy of timing analysis. We present a formula-based method to efficiently extract interconnect capacitances of interconnects
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::bed72e2a218aa06c022070b247cb330e
https://doi.org/10.1093/ietfec/e89-a.4.847
https://doi.org/10.1093/ietfec/e89-a.4.847