Zobrazeno 1 - 10
of 29
pro vyhledávání: '"Hironori Akamatsu"'
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:2109-2119
A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase
Autor:
T. Terano, Hirofumi Shinohara, Katsuji Satomi, Yasumasa Tsukamoto, Hironori Akamatsu, M. Kurumada, Makoto Yabuuchi, Shigeki Ohbayashi, S. Ishikura, H. Makino, T. Oashi, N. Kotani, Koji Nii, Y. Yamagami
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:938-945
We propose a new 2-port SRAM with a single read bit line (SRBL) eight transistors (8 T) memory cell for a 45 nm system-on-a-chip (SoC). Access time tends to be slower as a fabrication is scaled down because of threshold voltage (Vt) random variations
Autor:
H. Makino, Katsuji Satomi, S. Okazaki, Makoto Yabuuchi, S. Imaoka, Koji Nii, Hirofumi Shinohara, Akio Sebe, Shigeki Ohbayashi, Yasumasa Tsukamoto, T. Terano, K. Hashimoto, S. Ishikura, T. Oashi, Hironori Akamatsu, Y. Yamagami
Publikováno v:
IEEE Journal of Solid-State Circuits. 43:180-191
The variation tolerant assist circuits of an SRAM against process and temperature are proposed. Passive resistances are introduced to the read assist circuit with replica memory transistors to lower the wordline voltage accurately reflecting the proc
Autor:
Ichiro Hatanaka, Hiroyuki Yamauchi, Y. Yamagami, Akinori Shibayama, Toshikazu Suzuki, Hironori Akamatsu
Publikováno v:
IEEE Journal of Solid-State Circuits. 41:152-160
The mobile multi-media applications require to lower the operating voltage of embedded SRAMs. The ECC circuit implementation for increasing soft-error and the access timing control that tracks access delay fluctuation in memory core should be conside
Autor:
Hironori Akamatsu, Y. Yamagami, Ichiro Hatanaka, Akinori Shibayama, Hiroyuki Yamauchi, Toshikazu Suzuki
Publikováno v:
IEICE Transactions on Electronics. :630-638
This paper describes the access-timing control for an embedded SRAM core which operates in low and wide supply voltage (V dd = 0.3-1.5 V). In the conventional SRAMs, a wiring-replica with replica-memory-cell (RMC) to trace (he delay of memory core is
Publikováno v:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 5:377-387
This paper proposes a 0.5 V/100 MHz/sub-5 mW-operated 1-Mbit SRAM cell architecture which uses a boosted and offset-grounded data storage (BOGS) scheme. The key target of BOGS is to minimize the charge amount supplied from the embedded charge pump ci
Autor:
T. Fujita, Y. Shibata, T. Fujii, Junji Hirase, T. Hori, Toru Iwata, Hironori Akamatsu, N Shimizu, T. Tsuji, K. Yamashita, Hisakazu Kotani, Y. Naito, Yoshito Itoh, H. Asaka
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:1310-1316
A 256-Mb DRAM with refresh-free-FIFO function for storage of moving pictures has been developed using 0.25-/spl mu/m CMOS technology. An operating current of 73 mA (reduction of 52% compared with a conventional circuit) has been achieved at 100 MHz b
Autor:
H. Kotani, Michihiro Inoue, J. Matsushima, T. Shiragasawa, T. Yamada, Hironori Akamatsu, S. Okada
Publikováno v:
IEEE Journal of Solid-State Circuits. 25:30-35
An 8-Mb (1-Mwords*8-b) dynamic RAM which utilizes a column direction drive sense amplifier to obtain low peak current is described. The power supply peak current is about one fourth of that for conventional circuits. The chip operates at 50-MHz and i
Publikováno v:
CICC
The logic operating voltage is required to suppress for the battery-operated slow application, while the minimum operating voltage of SRAM increase due to the increase in the random threshold-voltage (Vt) fluctuation of the cell transistor (Tr) and t
Autor:
Koji Nii, Shigeki Ohbayashi, H. Makino, Yasumasa Tsukamoto, N. Kotani, M. Kurumada, Hirofumi Shinohara, T. Oashi, Makoto Yabuuchi, T. Terano, Hironori Akamatsu, Y. Yamagami, Katsuji Satomi, S. Ishikura
Publikováno v:
2007 IEEE Symposium on VLSI Circuits.
We propose a new 2port (2P) SRAM with an 8T single-bit-line (SBL) memory cell for 45 nm SOCs. Access time tends to be slower as the device size is scaled down because of the random threshold-voltage variations. The Divided read Bit line scheme with S