Výsledky vyhledávání - "Hiroki Shinkawata"

Akademický článek

The Study of Plasma Induced Damage on 65-nm Silicon on Thin BOX Transistor

Autor: Yoshiki Yamamoto, Kazuhiko Segi, Shibun Tsuda, Hideki Makiyama, Takumi Hasegawa, Keiichi Maekawa, Hiroki Shinkawata, Tomohiro Yamashita

Publikováno v: IEEE Journal of the Electron Devices Society, Vol 7, Pp 825-828 (2019)

This paper reports new findings about the plasma-induced damage on silicon on thin buried oxide (BOX) transistor. The plasma charge collected by source or drain causes Vth shift, which depends on BOX thickness. In addition, the observation was made t

Externí odkaz: https://doaj.org/article/3b959f8b90d34fc6ad7bbb408fe5fe6f

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The study of Plasma Induced Damage on Silicon on Thin BOX

Autor: Hideki Makiyama, Hiroki Shinkawata, Takumi Hasegawa, Kazuhiko Segi, Tomohiro Yamashita, Yoshiki Yamamoto, Keiichi Maekawa, Shibun Tsuda

Publikováno v: 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

This paper reports new findings about the plasma induced damage on silicon on thin BOX. The plasma charge collected by source or drain causes Vth shift, which depends on BOX thickness. In addition, the plasma charge collected by gate also has same ef

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9d85b7bf0f6ff076f42584b79308e26a
https://doi.org/10.1109/s3s.2018.8640129

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Ultra-Low-Standby Power 6T Single-port and 8T Dual-port SRAMs on 65 nm Silicon-on-Thin-Box (SOTB) for Smart IoT Applications

Autor: Yoshiki Yamamoto, Shinji Tanaka, Hiroki Shinkawata, Yukiko Umemoto, Shiro Kamohara, Makoto Yabuuchi, Takumi Hasegawa, Kyoji Ito, Koji Nii, Yohei Sawada, Yoshihiro Shinozaki

Publikováno v: 2018 14th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT).

In 65-nm Silicon-on-Thin-Box (SOTB) technology, we demonstrate fully functional embedded 6T single-port (SP) SRAM and 8T dual-port (DP) SRAM for Smart Internet-of-Things (IoT) applications. By using back-bias (BB) control in the sleep mode, 13.72 nW/

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::03d35a7df99efc9cc0a2222bc20b0fbf
https://doi.org/10.1109/icsict.2018.8564844

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Time-dependent Vth shift of silicon on thin BOX under large back bias

Autor: Hiroki Shinkawata, Shinobu Okanishi, Hideki Makiyama, Yasuo Yamaguchi, Keiichi Maekawa, Yoshiki Yamamoto, Takumi Hasegawa

Publikováno v: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

This paper report that the time-dependent Vth shift of transistor with Silicon on thin BOX (SOTB) can happen under large back bias. It is caused by slow inversion at BOX/Substrate interface. We show the guideline to consider this phenomena for device

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::fefc627cd0e4e76662e45fde3a639b87
https://doi.org/10.1109/s3s.2017.8308738

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An implementation of 2RW dual-port SRAM using 65 nm Silicon-on-Thin-Box (SOTB) for smart IoT

Autor: Takumi Hasegawa, Makoto Yabuuchi, Shinji Tanaka, Kyoji Ito, Koji Nii, Hiroki Shinkawata, Shiro Kamohara, Yoshiki Yamamoto, Yohei Sawada, Yoshihiro Shinozaki

Publikováno v: 2017 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference (S3S).

An embedded 2-read/write (2RW) dual-port (DP) SRAM using 65-nm Silicon-on-Thin-Box (SOTB) is demonstrated. 25.85 nW/Mbit ultra-low standby power is observed by applying back-bias (BB) control in the sleep mode, reduced to 1/1000 compared to the norma

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::9d71102fca110bb670599d7d50a56901
https://doi.org/10.1109/s3s.2017.8309224

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A 65 nm 1.0 V 1.84 ns Silicon-on-Thin-Box (SOTB) embedded SRAM with 13.72 nW/Mbit standby power for smart IoT

Autor: Yoshiki Yamamoto, Shiro Kamohara, Shinji Tanaka, Takumi Hasegawa, Hiroki Shinkawata, Makoto Yabuuchi, Yoshihiro Shinozaki, Koji Nii

Publikováno v: 2017 Symposium on VLSI Circuits.

A 65-nm Silicon-on-Thin-Box (SOTB) embedded SRAM is demonstrated. By using back-bias (BB) control in the sleep mode, 13.72 nW/Mbit ultra-low standby power is observed, which is reduced to 1/1000 compared to the normal standby mode. The measured read

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_dedup___::300d3adcbbfbefc20bb35f49040498d8
https://doi.org/10.23919/vlsic.2017.8008581

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SOTB (Silicon on Thin Buried Oxide): More than Moore technology for IoT and Automotive

Autor: Hideki Makiyama, Yoshiki Yamamoto, Yasuo Yamaguchi, Hiroki Shinkawata, Shiro Kamohara, Takumi Hasegawa

Publikováno v: ICICDT

Ultra low power performance is indispensable for Micro Controller Unit (MCU) used as wireless sensor and communication nodes which needs battery maintenance free and energy harvesting operation in the Internet of things (IoT) era. The Silicon on Thin

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::80d1d2b9537216ebe119c945e11afc32
https://doi.org/10.1109/icicdt.2017.7993512

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Analysis of Soft Failures in Low-Resistance Interconnect Vias Using Doubly Nesting Arrays

Autor: Takio Ohno, Tomoaki Yoshizawa, Atsushi Tsuda, Hiroki Shinkawata, Shingo Sato

Publikováno v: IEEE Transactions on Semiconductor Manufacturing. 27:178-183

An addressable test structure array for detecting soft failures in interconnect vias was developed. Resistive elements exhibiting abnormally high resistance are detected, while suppressing the measurement time, using a doubly nesting array structure.

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::202dedb4b4960cb01018cf40a5e8e854
https://doi.org/10.1109/tsm.2014.2310239

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Comprehensive analysis of low-frequency noise variability components in bulk and fully depleted silicon-on-insulator metal–oxide–semiconductor field-effect transistor

Autor: Hiroki Shinkawata, Keiichi Maekawa, Tomohiro Yamashita, Yoshiki Yamamoto, Hideki Makiyama, Shiro Kamohara, Yasuo Yamaguchi, Kenichiro Sonoda, Shinobu Okanishi, Takumi Hasegawa

Publikováno v: Japanese Journal of Applied Physics. 57:04FD19

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::f27778e4ffee3da7557d4a1223973d99
https://doi.org/10.7567/jjap.57.04fd19

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Development of a compacted doubly nesting array in Narrow Scribe Line aimed at detecting soft failures of interconnect via

Autor: Yasuo Yamaguchi, Atsushi Tsuda, Nobuo Tsuboi, Hiroki Shinkawata, Shingo Sato

Publikováno v: Proceedings of the 2015 International Conference on Microelectronic Test Structures.

We introduce a new addressable test structure array using for mass production stage which is compacted doubly nesting array into Narrow Scribe Line which named as High sensitivity-Screening and Detection-decoder test structure in Scribe line (HSD-S).

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3a6a3c6eeab4b55e1874ae2e956cf927
https://doi.org/10.1109/icmts.2015.7106112

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