Zobrazeno 1 - 5
of 5
pro vyhledávání: '"Hirohito Kikukawa"'
Autor:
N. Kuroda, Miho Miura, Hirohito Kikukawa, Hiroyuki Yamauchi, Y. Agata, K. Egashira, T. Uchikoba, T. Kawasaki, K. Takahashi, M. Shirahama, S. Hashimoto, S. Honda, H. Sadakata, W. Abe, R. Nishihara
Publikováno v:
IEEE Journal of Solid-State Circuits. 40:1200-1207
This paper describes a standard CMOS process based on embedded DRAM macro with dual-port interleaved DRAM architecture (D/sup 2/RAM), which is suitable for the leading edge CMOS LSIs with both high-speed and large-scale memories on a chip. This macro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::e977d4dd17a36a514c39172d4a195f79
https://doi.org/10.1109/jssc.2005.845995
https://doi.org/10.1109/jssc.2005.845995
Autor:
M. Ishikawa, A. Shibayama, Shigeki Tomishima, M. Senoh, H. Tanizaki, Hideto Hidaka, M. Maruta, T. Inokuchi, T. Kawasaki, Tsukasa Ooishi, W. Abe, K. Takahashi, S. Sakamoto, Hirohito Kikukawa, H. Kato, Y. Fukushima, Takaharu Tsuji, M. Nirro, T. Uchikoba
Publikováno v:
IEEE Journal of Solid-State Circuits. 37:932-940
This paper describes the 32-Mb and the 64-Mb embedded DRAM core with high efficient redundancy, which is fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology. Core size of 18.9 mm/sup 2/ and cell efficiency of 51.3% for the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::4cf387261f9eb206aff81ba58ccaf6f1
https://doi.org/10.1109/jssc.2002.1015693
https://doi.org/10.1109/jssc.2002.1015693
Autor:
W. Abe, H. Tanizaki, Hirohito Kikukawa, T. Kawasaki, Takaharu Tsuji, H. Kato, Tsukasa Ooishi, M. Ishikawa, K. Takahashi, M. Maruta, Hideto Hidaka, S. Sakamoto, Y. Fukushima, T. Inokuchi, T. Uchikoba, Shigeki Tomishima, A. Shibayama, M. Niiro, M. Senoh
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:1728-1737
This paper describes a 32-Mb embedded DRAM macro fabricated using 0.13-/spl mu/m triple-well 4-level Cu embedded DRAM technology, which is suitable for portable equipment of MPEG applications. This macro can operate 230-MHz random column access even
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::d0f61e52cddcc2b9f9a83b4db7e194be
https://doi.org/10.1109/4.962295
https://doi.org/10.1109/4.962295
Autor:
Takaharu Tsuji, H. Tanizaki, M. Ishikawa, Hideto Hidaka, M. Niiro, K. Takahashi, Akinori Shibayama, M. Senoh, T. Uchikoba, Shigeki Tomishima, Hirohito Kikukawa, T. Inokuchi, Y. Fukushima, H. Kato, S. Sakamoto, M. Maruta, T. Ooishi, W. Abe, T. Kawasaki
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
Previous embedded DRAMs (eDRAMs) have the dual ports on the sense amplifier and wide I/O buses on memory arrays for high data rate in graphic controller chips. This causes decreased cell efficiency and increased power consumption in burst operation c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f440fc5a1978863c5657964ce56ec469
https://doi.org/10.1109/isscc.2001.912684
https://doi.org/10.1109/isscc.2001.912684
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