Zobrazeno 1 - 8
of 8
pro vyhledávání: '"Hiroharu Fujise"'
Publikováno v:
TRANSACTIONS OF THE JAPAN SOCIETY OF MECHANICAL ENGINEERS Series B. 62:2586-2589
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::51ec3382bf228c853e58ed6711d27cb9
https://doi.org/10.1299/kikaib.62.2586
https://doi.org/10.1299/kikaib.62.2586
Autor:
Takashi Murakami, Kazuhiro Takeda, Masaki Satake, Makoto Tominaga, Seiji Nakagawa, Shinpei Nakamura, Tatsuhiko Ema, Hiroharu Fujise, Yuriko Seino, Hiroki Yonemitsu, Yosuke Kitamura, Masafumi Asano, Makoto Ueki, Shoji Mimotogi, Seiji Nagahara, Shinichiro Nakagawa, Takayuki Uchiyama, Kazuhiro Takahata
Publikováno v:
Advances in Resist Materials and Processing Technology XXVI.
Resist process challenges for 32-nm node and beyond are discussed in this paper. For line and space (L/S) logic patterns, we examine ways to balance the requirements of resolution-enhancement techniques (RETs). In 32-nm node logic patterning, two-dim
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::1b4f629c7763ef0c9e260778577ff0d2
https://doi.org/10.1117/12.813498
https://doi.org/10.1117/12.813498
Autor:
Akiko Yamada, Shoji Mimotogi, Kotaro Fujii, Hiroki Yonemitsu, Akiko Nomachi, Tatsuhiko Ema, Shinichi Ito, Satoshi Nagai, Hiroharu Fujise, Yuriko Seino, Fukushima Takashi, Toshiaki Komukai, Koutarou Sho, Yosuke Kitamura, Tsukasa Azuma
Publikováno v:
Advances in Resist Materials and Processing Technology XXV.
Key issues of resist process design for 32nm node logic device were discussed in this paper. One of them is reflectivity control in higher 1.3NA regime. The spec for the reflectivity control is more and more severe as technology node advances. The ta
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6f0225e7d02a33f8f394c13337d5ebd1
https://doi.org/10.1117/12.771008
https://doi.org/10.1117/12.771008
Autor:
Katsura Miyashita, Masaki Satake, Katsuyoshi Kodera, Soichi Inoue, Kazuhiro Takahata, Hideaki Harakawa, Yosuke Kitamura, Hiroharu Fujise, Shoji Mimotogi, Koutaro Sho, Tatsuya Ishida, Tatsuhiko Ema, Kenji Yoshida, Suigen Kyoh, Kazutaka Ishigo, Masafumi Asano, Hideki Kanai, Takuya Kono, Akiko Nomachi
Publikováno v:
Optical Microlithography XXI.
We have designed the lithography process for 32nm node logic devices under th e 1.3NA single exposure conditions. The simulation and experimental results indicate that the minimum pitches should be determined as 100nm for line pattern and 120nm for c
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f963acc1eddb32aedb38f145a206a9b3
https://doi.org/10.1117/12.772201
https://doi.org/10.1117/12.772201
Autor:
Koutaro Sho, Mikio Katsumata, Taiki Kimura, Shoji Mimotogi, Tatsuhiko Ema, Seiji Nagahara, Fumikatsu Uesawa, Makoto Tominaga, Hiroki Hane, Hiroharu Fujise, Atsushi Ikegami, Masafumi Asano, Hideki Kanai, M. Iwai
Publikováno v:
SPIE Proceedings.
Immersion lithography was applied to 45nm node logic and 0.25um 2 ultra-high density SRAM. The predictable enhancement of focus margin and resolution were obtained for all levels which were exposed by immersion tool. In particular, the immersion lith
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::024f73f27729ff65e39735aaf462d95a
https://doi.org/10.1117/12.711049
https://doi.org/10.1117/12.711049
Autor:
Tomohiro Sugiyama, Suigen Kyoh, Kohji Hashimoto, Shoji Mimotogi, Hideki Kanai, Maki Miyazaki, Eishi Shiobara, Kazuya Sato, Fumikatsu Uesawa, Kazuhiro Takahata, Koutaro Sho, Hiroki Hane, Hiroharu Fujise, Mikio Katsumata
Publikováno v:
Optical Microlithography XVIII.
In 45nm-node CMOS, the k1 value is around 0.35. In the low-k1 lithography, the robust design for lens aberration and process fluctuation such as mask CD error is required for manufacturing. The technologies of robust design for 45nm-node CMOS are pro
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b2dbee629174dc6c5f29b413ad5d0c60
https://doi.org/10.1117/12.600948
https://doi.org/10.1117/12.600948
Publikováno v:
SPIE Proceedings.
Tolerance-based process proximity correction (PPC) verification methodology is proposed for “hot spot management” in LSI fabrication process flow. This methodology verifies the PPC accuracy with the features of actual processed wafers/masks and t
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::92d7fe0f567dd782eec770b65b2fe40e
https://doi.org/10.1117/12.557795
https://doi.org/10.1117/12.557795
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