Zobrazeno 1 - 10
of 48
pro vyhledávání: '"Hing Yong"'
Autor:
Elizabeth Yong, Kun Hing Yong
Publikováno v:
Contabilitate şi Informatică de Gestiune, Vol 22, Iss 4, Pp 746-754 (2023)
This pitching research letter (PRL) describes the application of the pitching research template introduced by Faff (2015, 2021) to a reverse-engineering process in the practice of electronic fetal monitoring (EFM) as a form of defensive medicine with
Externí odkaz:
https://doaj.org/article/81f943241da149c5ad5dd21f25af5d5d
Autor:
Yen Nee Teo, Kun Hing Yong
Publikováno v:
Contabilitate şi Informatică de Gestiune, Vol 22, Iss 4, Pp 755-762 (2023)
The pitch template introduced by Faff (2015; 2021) has become increasingly popular in academic research. Therefore, this paper aims to offer readers new ideas about a more time-efficient and easy-to-understand way of exploring a new research area and
Externí odkaz:
https://doaj.org/article/68979125ce3a42bdb5f8cdd41d8555b3
Autor:
Yong, Elizabeth1, Kun Hing Yong2 kunhing.yong@griffithuni.edu.au
Publikováno v:
Journal of Accounting & Management Information Systems / Contabilitate si Informatica de Gestiune. 2023, Vol. 22 Issue 4, p746-755. 10p.
Autor:
Kun Hing Yong, Cordia Chu
Publikováno v:
Contabilitate şi Informatică de Gestiune, Vol 22, Iss 1, Pp 173-180 (2023)
The pitch template initiated by Faff (2015, 2021) is employed in this pitching research letter (PRL) for my PhD research topic. It not only facilitates a systematic approach for researchers to articulate a research idea critically but also aids new P
Externí odkaz:
https://doaj.org/article/23da02b7fe4b45219e5a7f712024ac00
Autor:
Tze Chiang Tin, Saw Chin Tan, Hing Yong, Jimmy Ook Hyun Kim, Eric Ken Yong Teo, Ching Kwang Lee, Peter Than, Angela Pei San Tan, Siew Chee Phang
Publikováno v:
IEEE Access, Vol 9, Pp 65418-65439 (2021)
Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and imprac
Externí odkaz:
https://doaj.org/article/383f69dab4b14d2a8853e07d64626e36
Autor:
Tze Chiang Tin, Saw Chin Tan, Hing Yong, Jimmy Ook Hyun Kim, Eric Ken Yong Teo, Joanne Ching Yee Wong, Ching Kwang Lee, Peter Than, Angela Pei San Tan, Siew Chee Phang
Publikováno v:
IEEE Access, Vol 9, Pp 114255-114266 (2021)
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to es
Externí odkaz:
https://doaj.org/article/1af0ef8f16bd4ef98eb015984544eed7
Autor:
Kun Hing Yong
Publikováno v:
Contabilitate şi Informatică de Gestiune, Vol 18, Iss 1, Pp 126-132 (2019)
This pitch letter summarizes my personal reflections of employing the pitching research template created by Faff (2015, 2018) to my PhD research topic. It explains how the template guides the author to articulate and conceptualize a research idea cri
Externí odkaz:
https://doaj.org/article/f2d39ccc52c847b494764bae1ad3af27
Publikováno v:
International Journal of Environmental Research and Public Health; Volume 20; Issue 10; Pages: 5910
Global climate change has contributed to the intensity, frequency, and duration of heatwave events. The association between heatwaves and elderly mortality is highly researched in developed countries. In contrast, heatwave impact on hospital admissio
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::d84f25bcf5c1da585aee1d7155e229b9
Autor:
Eric Ken Yong Teo, Siew Chee Phang, Hing Yong, Saw Chin Tan, Ching Kwang Lee, Tze Chiang Tin, Peter Than, Jimmy Ook Hyun Kim, Angela Pei San Tan
Publikováno v:
IEEE Access, Vol 9, Pp 65418-65439 (2021)
Integrated circuits (IC) are fabricated on a wafer through stacked layers of circuit patterns. To ensure proper functionality, the overlay of each pattern layer must be within the tolerance. Inspecting each wafer’s overlay is unrealistic and imprac
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c6f82358c9fbfe8313ffbb276d4e3fff
https://doi.org/10.1109/access.2021.3076193
https://doi.org/10.1109/access.2021.3076193
Autor:
Jimmy Ook Hyun Kim, Ching Kwang Lee, Tze Chiang Tin, Hing Yong, Joanne Ching Yee Wong, Peter Than, Saw Chin Tan, Angela Pei San Tan, Siew Chee Phang, Eric Ken Yong Teo
Publikováno v:
IEEE Access, Vol 9, Pp 114255-114266 (2021)
Virtual metrology (VM) is an enabling technology capable of performing virtual inspection on the metrology quality of wafers. Instead of physically acquiring the metrology measurements, VM applies conjecture models on the process data of wafers to es
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::c07088dc03d1bbb4694fe965ea5970ee
https://doi.org/10.1109/access.2021.3103235
https://doi.org/10.1109/access.2021.3103235