Výsledky vyhledávání - "Himani Kamineni"

A Generic Strategy to Assess and Mitigate Chip Package Interaction Risk Factors for Semiconductor Devices with Ultra-low k Dielectric Materials in Back End of Line

Autor: Kashi Vishwanath Machani, Dirk Breuer, Christian Klewer, Christian Goetze, Holm Geisler, Bjoern Boehme, Himani Kamineni, Michael Thiele, Michael Hecker, Jae Kyu Cho, Frank Kuechenmeister, Jens Paul

Publikováno v: International Symposium on Microelectronics. 2017:000163-000171

This paper describes a systematic approach to the identification of primary contributing factors to the Chip Package Interaction (CPI) risk and reveals the mitigation strategy successfully applied by GLOBALFOUNDRIES. The strategy includes modeling at

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2a43a8b7ef77a9c83756f0e58d23f776
https://doi.org/10.4071/isom-2017-wa12_066

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Utilizing Thermo-Mechanical CPI Simulation to Define a 7nm Package Envelope

Autor: Himani Kamineni, Thiagarajan Raman, Scott Pozder, Carole Graas

Publikováno v: 2018 7th Electronic System-Integration Technology Conference (ESTC).

The objective of this work is to use simulation results of a back end of line (BEOL) construction known to be susceptible to white bump failure to predict Chip package interaction (CPI) failure risk of other designs, prior to running a reliability qu

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::32d8b756ecb17eea556cbfbcfda1d486
https://doi.org/10.1109/estc.2018.8546392

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A New Type of TSV Defect Caused by BMD in Silicon Substrate

Autor: Mark Scholefield, Dingyou Zhang, Tong Qing Chen, Sarasvathi Thangaraju, Wonwoo Kim, Ming Lei, Christian Klewer, Kumarapuram Gopalakrishnan, Daniel Smith, Abhishek Vikram, Himani Kamineni, Victor Lim, Ramakanth Alapati

Publikováno v: Additional Conferences (Device Packaging, HiTEC, HiTEN, and CICMT). 2014:001506-001522

This paper reports on a new type of through-silicon via (TSV) defect, silicon fin defect, which was found after TSV deep-reactive-ion-etching (DRIE) process for TSV integration with front-end-of-line (FEOL) devices. One possible root cause for this d

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::3476245113154b36ceb2b3146c91c946
https://doi.org/10.4071/2014dpc-wp14

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BMD impact on silicon fin defect at TSV bottom

Autor: Dingyou Zhang, Mark Scholefield, Christian Klewer, Wonwoo Kim, Ramakanth Alapati, Abhishek Vikram, Himani Kamineni, Ming Lei, Daniel Smith, Sarasvathi Thangaraju, Victor Lim

Publikováno v: Electronics Letters. 50:954-956

A new type of through-silicon via (TSV) defect, silicon fin defect, which was found after the TSV deep-reactive-ion-etching process at the TSV bottom is reported. These defects are considered killer TSV defects that may cause process or mechanical fa

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::2209ce57a316b12d98feffb442d83b4c
https://doi.org/10.1049/el.2014.0974

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New interferometric measurement technique for small diameter TSV

Autor: Dingyou Zhang, Hemant Amin, Sarasvathi Thangaraju, Himani Kamineni, Ramakanth Alapati, Alok Vaid, Jonathan Peak, Wonwoo Kim, Nigel Smith, Timothy Norman Johnson, Brennan Peterson, Ke Xiao, Yeong-Uk Ko, Holly Edmundson, Padraig Timoney, Daniel Smith, Daniel Fisher

Publikováno v: 25th Annual SEMI Advanced Semiconductor Manufacturing Conference (ASMC 2014).

High aspect ratio through silicon vias (TSV) present a challenge for measurement of bottom critical dimension (BCD) and depth. TSVs smaller than 5 micron diameter with greater than 12:1 depth to BCD aspect ratio have particularly poor signal to noise

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::b77d25fc1b78b571329aa3c8813595b1
https://doi.org/10.1109/asmc.2014.6846973

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Challenges to via middle TSV integration at sub-28nm nodes

Autor: Himani Kamineni, Dingyou Zhang, Daniel Smith, Sukeshwar Kannan, Shan Gao, Ramakanth Alapati, Sarasvathi Thangaraju

Publikováno v: IEEE International Interconnect Technology Conference.

This work presents the via middle TSV integration at sub-28 nm nodes using a new local interconnect scheme involving V0 vias. Various V0 schemes are presented along with their respective resistance, capacitance and leakage current data. The character

Externí odkaz: https://explore.openaire.eu/search/publication?articleId=doi_________::4c2c8fc566b763d31fc4780a9c1527ca
https://doi.org/10.1109/iitc.2014.6831869

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