Zobrazeno 1 - 10
of 22
pro vyhledávání: '"Himadri Singh Raghav"'
Publikováno v:
2022 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits).
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::8e948b1d255d0f33ed4cbc013e786018
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830158
https://doi.org/10.1109/vlsitechnologyandcir46769.2022.9830158
Autor:
Himadri Singh Raghav, Izzet Kale
Publikováno v:
Integration. 69:147-160
The existing Power Analysis Attacks (PAA) resilient adiabatic logic designs exhibit variations in current peaks, have asymmetric structures and suffer from Non-Adiabatic Losses (NAL) during the evaluation phase of the power-clock. However, asymmetric
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::edd8f202e4a7fd3d5adcbff3b8023459
https://doi.org/10.1016/j.vlsi.2018.07.010
https://doi.org/10.1016/j.vlsi.2018.07.010
Publikováno v:
PATMOS
On the whole existing secure adiabatic logic designs exhibit variations in current peaks and have asymmetric structures. However, asymmetric structure and variations in current peaks make the circuit vulnerable to Power Analysis Attacks (PAA). In thi
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2b1c6fbf7457ba4c0a4ab64f1db38094
https://doi.org/10.1109/patmos.2018.8463996
https://doi.org/10.1109/patmos.2018.8463996
Existing secure adiabatic logic designs use charge sharing inputs to deliver input independent energy dissipation and suffer from non-adiabatic losses (NAL) during the evaluation phase of the power-clock. However, using additional inputs present the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::e2a3776f762d70c34fb0be57619b532c
https://doi.org/10.1016/j.mejo.2018.04.004
https://doi.org/10.1016/j.mejo.2018.04.004
Publikováno v:
PATMOS
In this paper, we propose Without Charge Sharing Quasi Adiabatic Logic (WCS-QuAL) as a countermeasure against Power Analysis Attacks. We evaluate and compare our logic with the recently proposed secure adiabatic logic designs SPGAL and EE-SPFAL at fr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c5fe92b41c46460e5fdb54e197426d15
https://doi.org/10.1109/patmos.2017.8106968
https://doi.org/10.1109/patmos.2017.8106968
Publikováno v:
ECCTD
In this paper, we propose a novel power analysis attack resilient adiabatic logic which, unlike existing secure adiabatic logic designs doesn't require any charge sharing between the output nodes of the gates. The proposed logic also dissipates less
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::c1a1ef0bae581fdc04c116cce49e7ac8
https://doi.org/10.1109/ecctd.2017.8093262
https://doi.org/10.1109/ecctd.2017.8093262
Publikováno v:
PATMOS
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider the energy efficiency of a 2-step charging strategy based on a single tank-capacitor circuit. We have investigated the impact of various parame
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3ad7a672398b0866fd1491174e07ee0c
https://doi.org/10.1109/patmos.2016.7833684
https://doi.org/10.1109/patmos.2016.7833684
Publikováno v:
2016 12th Conference on Ph.D. Research in Microelectronics and Electronics (PRIME).
The generation of power-clocks in adiabatic integrated circuits is investigated. Specifically, we consider stepwise charging strategies (2, 3, 4, 5, 6, 7, and 8-step) based on tank-capacitor circuits, comparing them in terms of their energy recovery
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::638b7e229c0855402d7b537575deefe6
https://doi.org/10.1109/prime.2016.7519499
https://doi.org/10.1109/prime.2016.7519499
Publikováno v:
2013 Annual International Conference on Emerging Research Areas and 2013 International Conference on Microelectronics, Communications and Renewable Energy.
This paper deals with the design of a low power signal conditioning circuit for use in biomedical applications. The signal conditioning circuit constitutes an opamp serving as a preamplifier and a low-pass filter for rejecting higher frequency compon
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::314c8b3f27e8c0a9acffc8a2f8b981a9
https://doi.org/10.1109/aicera-icmicr.2013.6576034
https://doi.org/10.1109/aicera-icmicr.2013.6576034
Publikováno v:
Communications in Computer and Information Science ISBN: 9783642420238
VDAT
VDAT
In this paper, an effort has been made to improve the delay of a gate by skewing the gates by choosing proper sizing. The expression for skewed logical effort has been derived for universal logic gates namely NOT, NAND and NOR for minimizing the dela
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::6c808c5a40ae6f65e8c996f7b6ce5b5e
https://doi.org/10.1007/978-3-642-42024-5_14
https://doi.org/10.1007/978-3-642-42024-5_14