Zobrazeno 1 - 10
of 76
pro vyhledávání: '"High-Speed Serial Interface"'
Publikováno v:
IEEE Access, Vol 10, Pp 21187-21192 (2022)
This paper describes a packet-based overhead-reduced (OR) key coding technique for a high-speed serial interface. The 8B10B code is a de facto standard coding technique in the application but its bit-overhead is 25%. The proposed key coding technique
Externí odkaz:
https://doaj.org/article/311d13d87fbe4ea9b2b5fc302a4a5fa7
Publikováno v:
Dianzi Jishu Yingyong, Vol 44, Iss 8, Pp 47-51 (2018)
High performance data converter is the core device of the fifth generation mobile communication base station system. Its sampling rate is no less than 3 GS/s and the resolution is higher than 12 bit. Therefore, it is inevitable for high-speed serial
Externí odkaz:
https://doaj.org/article/b98fec66041243b7b6339c2711cbcc0d
Autor:
Xuqiang Zheng, Lei Zhou, Dechao Lu, Jian Luan, Yong Chen, Xinyu Liu, Danyu Wu, Chen Cai, Jin Wu
Publikováno v:
Electronics
Volume 10
Issue 16
Electronics, Vol 10, Iss 1873, p 1873 (2021)
Volume 10
Issue 16
Electronics, Vol 10, Iss 1873, p 1873 (2021)
This paper presents a fully integrated physical layer (PHY) transmitter (TX) suiting for multiple industrial protocols and compatible with different protocol versions. Targeting a wide operating range, the LC-based phase-locked loop (PLL) with a dual
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_dedup___::1f6cdad2eb295a2fc799cf083e5ffd6a
Publikováno v:
2021 IEEE 4th Advanced Information Management, Communicates, Electronic and Automation Control Conference (IMCEC).
With the continuous development of optical communication, the transmission rate and bandwidth of optical fiber signals are also increasing. The acquisition system with single-chip ADC and FPGA can no longer meet the needs of high speed and large band
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::31c2c8fe85609e34b94fcaec481bd43d
https://doi.org/10.1109/imcec51613.2021.9482074
https://doi.org/10.1109/imcec51613.2021.9482074
Autor:
JinHwan Kim, Seung-Taek Lee, GeonGu Park, NamHyuk Yang, Sangwoo Pae, Hoosung Kim, Sang-Won Hwang, ChulHyuk Kwon
Publikováno v:
IRPS
With the development of high speed serial interface technology, data transmission speed is increasing and it is important to secure the signal transmission quality. In particular, in the case of smartphones, as the 5G network era arrives, the data tr
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::45615638b2e9e22e21ecf8860b907b10
https://doi.org/10.1109/irps46558.2021.9405096
https://doi.org/10.1109/irps46558.2021.9405096
Autor:
Beom-Kyu Seo, Hyun-Woo Kim, Hyung-Tae Kim, Yeoun-Sook Shin, Young-dae Kim, Sang-Uck Ahn, Ghil-Geun Oh
Publikováno v:
ITC
In High-Speed Serial Interface (HSSI) IP using AC coupled configuration, due to the AC coupled configuration, it can cause unexpected issues that cannot screen fail chips. That is, external loopback test is not able to reject the fail chip, even if o
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::af61be83189b9a3afea698266903f0c0
https://doi.org/10.1109/itc44778.2020.9325235
https://doi.org/10.1109/itc44778.2020.9325235
Publikováno v:
2020 IEEE 3rd International Conference on Electronics Technology (ICET).
Using single event effect sensitivity evaluation test method and test system as well as pulsed laser simulation sources, the SEE sensitivity of High-Speed Serial Interface was experimentally researched. The test results show that the JESD204B high-sp
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f348d986e0bcb2cc62e16129c517319a
https://doi.org/10.1109/icet49382.2020.9119539
https://doi.org/10.1109/icet49382.2020.9119539
Akademický článek
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Publikováno v:
Integration. 57:101-107
A jitter tolerance calibration test bench suitable for high speed serial interfaces (HSSI) using verilog-AMS is proposed in this paper. The jitter tolerance simulation environment can be easily parameterized in order to be compliant to any HSSI stand
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::a0450be366b3842dd95097f181e6504c
https://doi.org/10.1016/j.vlsi.2016.12.008
https://doi.org/10.1016/j.vlsi.2016.12.008
Publikováno v:
2019 International SoC Design Conference (ISOCC).
— An eye-open monitoring system based on signal counting is introduced. Data is sampled 2048 times and "0" or "1" is counted to determine eye-opening at each sampling point. The FPGA stores the counter value and outputs the estimated eye-diagram. T
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::0e78b599e3e45d8576d7a3c707ce0f08
https://doi.org/10.1109/isocc47750.2019.9078519
https://doi.org/10.1109/isocc47750.2019.9078519