Zobrazeno 1 - 10
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pro vyhledávání: '"High-Level Synthesis"'
Autor:
H. N., Mahendra1 mahendrahn@jssateb.ac.in, S., Mallikarjunaswamy1 mallikarjunaswamys@jssateb.ac.in
Publikováno v:
International Journal of Electronics & Telecommunications. 2022, Vol. 68 Issue 3, p609-617. 9p.
Publikováno v:
International Journal of Electronics and Telecommunications, Vol vol. 70, Iss No 4 (2024)
This paper explores advanced techniques in highlevel synthesis (HLS) utilizing metamodel structures. Metamodels act as models of hardware models, generating internal hardware models based on parameter inputs and exploring the solution space to find o
Externí odkaz:
https://doaj.org/article/aafc9df0ad804c79bb46d7b271c1edfa
Publikováno v:
Proceedings of the International Multidisciplinary Scientific GeoConference SGEM. 2018, Vol. 18, p453-460. 8p.
Akademický článek
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Hybrid Graph Representation and Learning Framework for High-Level Synthesis Design Space Exploration
Publikováno v:
IEEE Access, Vol 12, Pp 189574-189589 (2024)
Optimizing hardware accelerators in high-level synthesis (HLS) relies on design space exploration (DSE), which involves experimenting with different pragma options and trading off hardware cost and performance metrics (HCPMs) to identify Pareto-optim
Externí odkaz:
https://doaj.org/article/75c0eadd72d94c3c93ee39758723e435
Autor:
Dhilleswararao Pudi, Yu Yang, Dimitrios Stathis, Sunil Kumar Prajapati, Srinivas Boppu, Ahmed Hemani, Linga Reddy Cenkeramaddi
Publikováno v:
IEEE Access, Vol 12, Pp 155885-155903 (2024)
Efficiently synthesizing an entire application that consists of multiple algorithms for hardware implementation is a very difficult and unsolved problem. One of the main challenges is the lack of good algorithmic libraries. A good algorithmic library
Externí odkaz:
https://doaj.org/article/d5da1297f8574bae87ac797fa1f57b5c
Autor:
Dhilleswararao Pudi, Shivam Malviya, Srinivas Boppu, Yu Yang, Ahmed Hemani, Linga Reddy Cenkeramaddi
Publikováno v:
IEEE Access, Vol 12, Pp 124081-124094 (2024)
Coarse-Grained Reconfigurable Array (CGRA) architectures are potential high-performance and power-efficient platforms. However, mapping applications efficiently on CGRA, which includes scheduling and binding operations on functional units and variabl
Externí odkaz:
https://doaj.org/article/90e050bb4b894cbb8272c59e66c4744d
Publikováno v:
IEEE Access, Vol 12, Pp 72813-72827 (2024)
Image dehazing is a crucial task in the early stages of real-time image processing pipelines used in applications such as surveillance and advance driver assistance systems. Dehazing algorithms mitigate the spatially selective degradation of image de
Externí odkaz:
https://doaj.org/article/79cd0e0717594b518a3823970ca5cf91
Autor:
Dionysios Filippas, Christodoulos Peltekis, Vasileios Titopoulos, Ioannis Kansizoglou, Georgios CH. Sirakoulis, Antonios Gasteratos, Giorgos Dimitrakopoulos
Publikováno v:
IEEE Access, Vol 12, Pp 57194-57208 (2024)
Convolution neural networks (CNNs) are widely applied in many machine learning applications. Hardware acceleration for CNNs is crucial, given their high computational intensity and the demand for enhanced energy efficiency and reduced latency in appl
Externí odkaz:
https://doaj.org/article/33c1766733254d368409fdccc04d5072
Publikováno v:
IEEE Journal of Selected Topics in Applied Earth Observations and Remote Sensing, Vol 17, Pp 8230-8249 (2024)
On-board processing has become an inevitable choice for the development of remote-sensing satellites. For the satellites with dual-line array asynchronous push-broom mode, image registration is crucial for pixel localization and alignment between dua
Externí odkaz:
https://doaj.org/article/990d0b37c5104c188e444d4c3835cc85