Zobrazeno 1 - 10
of 27
pro vyhledávání: '"Hideyuki Ozaki"'
Autor:
Akira Yamazaki, Atsushi Hachisuka, Katsumi Dosaka, Tsutomu Yoshihara, Teruhiko Amano, Hideyuki Ozaki, Naoya Watanabe, Hideyuki Noda, Masaru Haraguchi, Kazutami Arimoto, Fukashi Morishita, Setsuos Wake
Publikováno v:
IEICE Transactions on Electronics. :2020-2027
The voltage margin of an embedded DRAM's sense operation has been shrinking with the scaling of process technology. A method to estimate this margin would be a key to optimizing the memory array configuration and the size of the sense transistor. In
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::2164b4ddefa9f4233c32a65d7e165ef9
https://doi.org/10.1093/ietele/e88-c.10.2020
https://doi.org/10.1093/ietele/e88-c.10.2020
Autor:
T. Yoshihara, M. Kinoshita, Michihiro Yamada, Katsumi Dosaka, Kazutami Arimoto, Hideyuki Ozaki, T. Amano, Tadaaki Yamauchi
Publikováno v:
IEEE Journal of Solid-State Circuits. 36:46-54
This paper proposes the virtual-socket architecture in order to reduce the design turn-around time (TAT) of the embedded DRAM. The required memory density and the function of the embedded DRAM are system dependent. In the conventional design, the DRA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::58e9d85a427d9385a39cc942b56bba7d
https://doi.org/10.1109/4.896228
https://doi.org/10.1109/4.896228
Autor:
Kazutami Arimoto, Hideyuki Ozaki, T. Yoshihara, S. Maeda, T. Yamauchi, F. Morisita, Kazuyasu Fujishima
Publikováno v:
IEEE Journal of Solid-State Circuits. 35:1169-1178
This paper presents the high-performance DRAM array and logic architecture for a sub-1.2-V embedded silicon-on-insulator (SOI) DRAM. The degradation of the transistor performance caused by boosted wordline voltage level is distinctly apparent in the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::b46ebdd598048f6451e892360c1f3797
https://doi.org/10.1109/4.859506
https://doi.org/10.1109/4.859506
Autor:
Tsukasa Ooishi, Kiyohiro Furutani, Hideyuki Ozaki, Kei Hamade, Hideto Hidaka, Kenichi Yasuda, Tetsuo Kato, Mikio Asakura, Yuichiro Komiya
Publikováno v:
IEEE Journal of Solid-State Circuits. 31:575-585
This paper proposes a low voltage operation technique for a voltage down converter (VDC) using a mixed-mode VDC (MM-VDC), that combines an analog VDC and a digital VDC, and provides high frequency application using an impedance adjustment circuitry (
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::eb73aedc2d1e2235bbfedf3735dcda30
https://doi.org/10.1109/4.499735
https://doi.org/10.1109/4.499735
Autor:
Kiyohiro Furutani, Hideyuki Ozaki, Yuichiro Komiya, Mikio Asakura, Tsukasa Ooishi, Hideto Hidaka, Kenichi Yasuda, Kei Hamade, Hiroshi Miyamoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 30:471-479
This paper describes DRAM array driving techniques and the parameter scaling techniques for low voltage operation using the boosted sense ground (BSG) scheme and further improved methods. Temperature compensation and adjustable internal voltage level
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::225a498c6c3da2246ac34066d3d64299
https://doi.org/10.1109/4.375968
https://doi.org/10.1109/4.375968
Autor:
Kiyohiro Furutani, Y. Okasaka, Hiroshi Miyamoto, Yoshikazu Morooka, T. Kajimoto, Hideyuki Ozaki, Y. Tsukikawa
Publikováno v:
IEEE Journal of Solid-State Circuits. 29:534-538
An efficient back-bias (V/sub bb/) generator with a newly introduced hybrid pumping circuit (HPC) is described. This system attains a V/sub bb/ level of /spl minus/1.44 V at V/sub cc/=1.5 V, compared to a conventional system in which V/sub bb/ only r
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::102b5246a1a201df6e24574a72addd09
https://doi.org/10.1109/4.280705
https://doi.org/10.1109/4.280705
Autor:
Hideyuki Ozaki, Tadato Yamagata, T. Kobayashi, Michihiro Yamada, Masaaki Mihara, Y. Murai, Takeshi Hamamoto
Publikováno v:
IEEE Journal of Solid-State Circuits. 27:1927-1933
A 288-kb (8 K words*36 b) fully parallel content addressable memory (CAM) LSI using a compact dynamic CAM cell with a stacked-capacitor structure and a novel hierarchical priority encoder is described. The stacked-capacitor structure results in a ver
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::3c083e3c0009af9d6442c4309a932011
https://doi.org/10.1109/4.173123
https://doi.org/10.1109/4.173123
Publikováno v:
Electronics and Communications in Japan (Part II: Electronics). 73:1-9
This paper discusses a CMOS row decoder, which is indispensable to a VLSI DRAM. The factors involved in operational delay are analyzed and an investigation is done in order to be able to realize high-speed operation, while maintaining the feature of
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::f230597eaa248fc96e194b9728aa6f8c
https://doi.org/10.1002/ecjb.4420730301
https://doi.org/10.1002/ecjb.4420730301
Autor:
Katsuya Furue, Yoshihiro Nagura, Hideyuki Ozaki, Fukashi Morishita, Akira Yamazaki, Tatsunori Komoike, Tetsushi Tanizaki, F. Igaue, Atsushi Hachisuka, Y. Taito, Toshinori Morihara, Naoya Watanabe, Katsumi Dosaka, Yoshikazu Morooka, Kazutami Arimoto
Publikováno v:
2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).
Embedded DRAM (eDRAM) macros have been proposed as away to achieve the low power and wide bandwidth required by graphic controllers, network systems, and mobile systems. Currently, these applications require a reduction of design turn-around time (TA
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::7417683b8cb8ee5d171694e2fc4459ef
https://doi.org/10.1109/isscc.2001.912686
https://doi.org/10.1109/isscc.2001.912686
Autor:
S. Wake, Hiroki Shimano, Isamu Hayashi, Akira Yamazaki, M. Kobayashi, Hideyuki Noda, Hideyuki Ozaki, Katsumi Dosaka, Shinya Soeda, J. Ootani, Takeshi Fujino, Atsushi Hachisuka, Naoya Watanabe, Y. Okumura, K. Inoue, Yoshikazu Morooka, Fukashi Morishita, Kazutami Arimoto
Publikováno v:
2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).
Advanced 3D graphics (3DG) technology will be used in console game machines, and it is desired to develop a rendering controller chip which can handle real time 3D animation with true colors. Embedded DRAM (eDRAM) technology attracts attention of the
Externí odkaz:
https://explore.openaire.eu/search/publication?articleId=doi_________::627c0c708dfa177263d2bb2ebe94c109
https://doi.org/10.1109/isscc.2000.839830
https://doi.org/10.1109/isscc.2000.839830