Zobrazeno 1 - 10
of 54
pro vyhledávání: '"Hideyuki Ichihara"'
Publikováno v:
2022 IEEE International Test Conference in Asia (ITC-Asia).
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :1464-1471
Publikováno v:
2021 IEEE 30th Asian Test Symposium (ATS).
Publikováno v:
DFT
Stochastic computing (SC) has attractive characteristics such as smaller area and lower power than deterministic (or general binary) computing. A SC circuit design scheme based on linear finite state machines (linear FSMs) has been proposed for reali
Publikováno v:
IEEE Transactions on Emerging Topics in Computing. 7:31-43
Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention as an alternative to deterministic computing. In this paper, we discuss a design method for compact and accurate digital filters based on SC. S
Publikováno v:
DFT
Stochastic computing (SC) has attractive characteristics, compared with deterministic (or general binary) computing, such as smaller area of the implemented circuits, higher fault tolerance and so on. This study focuses on the transient fault toleran
Publikováno v:
ITC-Asia
Register-transfer level (RTL) scan design aims at optimizing the scan logic as well as the original logic during logic synthesis by modifying a given RTL description to make every register scannable. The modified RTL description, however, is not uniq
Publikováno v:
ITC-Asia
Stochastic computing (SC), which is an approximate computation with probabilities, has attracted attention owing to its small area, small power consumption and high fault tolerance. In this paper, we focus on the fault tolerance of SC with linear fin
Publikováno v:
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences. :2571-2578
In this paper, we propose a hybrid test application in partial skewed-load (PSL) scan design. The PSL scan design in which some flip-flops (FFs) are controlled as skewed-load FFs and the others are controlled as broad-side FFs was proposed in [1]. We
Publikováno v:
IEICE Transactions on Information and Systems. :1549-1559
We present a graph model and an ILP model for TAM design for transparency-based SoC testing. The proposed method is an extension of a previous work proposed by Chakrabarty with respect to the following three points: (1) constraint relaxation by consi